mem: Add prefetch requests to the arbitration logic of MSHR.

[Ergou-ren]

Change-Id: I45c4b62c0c4c77b574a8f06da7b7b27104027320

1. At the last 1 tick of each cycle, process the prefetch requests to ensure the prefetch has the lowest priority.
2. The prefetch request enters the mshr to participate in arbitration.

[XiangShanRobot]

[Generated by GEM5 Performance Robot]
commit: ad948c4
workflow: gem5 Ideal BTB Performance Test

Ideal BTB Performance

Overall Score

	PR	Master	Diff(%)
Score	19.84	19.85	-0.04 🔴

[XiangShanRobot]

[Generated by GEM5 Performance Robot]
commit: ad948c4
workflow: gem5 Performance Test

Standard Performance

Overall Score

	PR	Master	Diff(%)
Score	16.18	16.20	-0.15 🔴

[XiangShanRobot]

[Generated by GEM5 Performance Robot]
commit: ad948c4
workflow: gem5 Ideal BTB Performance Test (no SC)

Ideal BTB Performance

Overall Score

	PR	Master	Diff(%)
Score	19.49	19.47	+0.12 🟢