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Open-source high-performance RISC-V processor
Scala 6.7k 826
Documentation for XiangShan
Markdown 426 146
Open-source high-performance non-blocking cache
Scala 90 41
Modern co-simulation framework for RISC-V CPUs
C++ 159 86
XiangShan Frontend Develop Environment
Shell 68 60
Super fast RISC-V ISA emulator for XiangShan processor
C 295 113
This repo includes XiangShan's function units
Open-source non-blocking L2 cache
Documentation for XiangShan Design
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XiangShan Tutorial Website
XiangShan bootcamp
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