fpga: Change default burst for xilinx ips #34
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Removing one problematic parameter (should not be Resp=RESP_OKAY in the axi error slave) Redefining the pop signal for a FIFO, which was faultly popping data from an empty FIFO, activating the assertions.
Included the assert header into the regmap file requiring the ASSERT macros.
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When using certain Xilinx IPs, the burst type FIXED is not supported. In practice, they are not used (len=0) anyways.
AXI SmartConnect product guide (PG247):