IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.

Innervator: Hardware Acceleration for Neural Networks

An implementation of the LC-3 architecture in VHDL, as described in the book "Introduction to Computing Systems by P&P".

A comprehensive collection of VHDL designs for digital circuits, organized by category and featuring a complete test suite with automated CI/CD

This respositort contains all vhdl codes and simulations of final year vlsi lab of NIT Rourkela

A pedagogical processor on FPGA, developed at NIIT University.

Design of an arithmetic logic (ALU). It typically performs mathematical and logical functions. An ALU is designed and implemented using VHDL.

Verilog code practice using the Xilinx Vivado design suite

VHDL implementation of an "asynchronous" FIFO with 64 positions of 8-bit words. Features dual clock domains (wr_clk, rd_clk), asynchronous reset, status signals (empty, full, almost empty/full, error), testbench, synthesis scripts, and timing/power/area reports.

Fast VHDL language server written in Rust

Mi Proyecto Integrador para obtener el título de Ingeniero Electrónico. Course completion assignment for Electronic Engineer Degree.

The project involves designing an 8-bit Arithmetic Logic Unit (ALU) using VHDL. The ALU performs eight different operations based on a 3-bit opcode, making it a fundamental component in digital circuits and processors. The implementation includes both the ALU module and a testbench to verify its functionality.

Codes for VHDL programming for VLSI designing.

VHDL implementation of a synchronous FIFO (First In First Out) with 64 positions of 8-bit words. Includes status signals (empty, full, almost empty/full, error), asynchronous reset, edge-sensitive read/write, testbench, synthesis scripts, and timing/power/area reports.