```SystemVerilog module top; parameter ENABLE = 1; if (ENABLE) begin : blk wire [7:0] w; end wire [7:0] x; wire [$bits(blk.w)-1:0] y; wire [$bits(x)-1:0] z; initial begin $display("blk.w: %b (%0d bits)", blk.w, $bits(blk.w)); $display("x: %b (%0d bits)", x, $bits(x)); $display("y: %b (%0d bits)", y, $bits(y)); $display("z: %b (%0d bits)", z, $bits(z)); end endmodule ``` When simulating the above test case, most tools produce: ``` blk.w: zzzzzzzz (8 bits) x: zzzzzzzz (8 bits) y: zzzzzzzz (8 bits) z: zzzzzzzz (8 bits) ``` However, iverilog (both version 11.0 and the latest master) produces: ``` blk.w: zzzzzzzz (8 bits) x: zzzzzzzz (8 bits) y: xx (0 bits) z: zzzzzzzz (8 bits) ``` Notice that `$bits(blk.w)` correctly evaluates to `8` in the `$display` call, but not in the declaration of `y`.