[x86 disassembler] arpl should not be possible with 64-bit target

[llvmbot]

Bugzilla Link	10700
Resolution	FIXED
Resolved on	Mar 01, 2012 12:25
Version	trunk
OS	All
Blocks	llvm/llvm-bugzilla-archive#10988
Reporter	LLVM Bugzilla Contributor
CC	@topperc,@efriedma-quic

Extended Description

From the "Intel® 64 and IA-32 Architectures Software Developer’s Manual
Volume 2 (2A & 2B): Instruction Set Reference, A-Z", p. 3-75:
ARPL—Adjust RPL Field of Segment Selector
63 /r
"This instruction executes as described in compatibility mode and legacy mode. It is not encodable in 64-bit mode."

P. 3-730 shows the encoding in 64-bit mode:
MOVSX/MOVSXD—Move with Sign-Extension
REX.W** + 63 /r

With llvm-mc built from trunk revision 135913:
$ echo '0x63 0xc0'| ./llvm-mc -disassemble -triple="x86_64"
arpl %ax, %ax

With the 64-bit target set, this should have disassembled as 'movsx'.

[llvmbot]

Sorry - it should've disassembled as 'movsxd' (not 'movsx') according to the Intel doc since the source is a doubleword (32-bit).

[efriedma-quic]

Sure... granted, no compiler will ever generate that instruction.

[llvmbot]

Sure... granted, no compiler will ever generate that instruction.

Agreed - but my intended use of the llvm disassembler is with more than just compiler-generated code.

[topperc]

r140370 fixes part of this so that the instruction won't decode as arpl anymore. That also fixed some other invalid instruction decodings including push/pop ss/ds/es/cs.

[topperc]

This will decode as MOVSXD if you set REX.W.

echo '0x48 0x63 0xc0'| ./llvm-mc -disassemble -triple="x86_64"
movslq %eax, %rax

Based on the the docs, I think maybe without the REX.W prefix it would only write the low 32-bits of the destination and 0 the upper bits. Effectively, making it equivalent to regular MOV. Not sure its worth making the disassembler support this since the docs say its discouraged.

[llvmbot]

Testing with r151510:
$ echo '0x63 0xc0' | ./llvm-mc -disassemble -triple=x86_64 :1:1: warning: invalid instruction encoding
0x63 0xc0
^
:1:6: warning: invalid instruction encoding
0x63 0xc0
^
$ echo '0x48 0x63 0xc0' | ./llvm-mc -disassemble -triple=x86_64
movslq %eax, %rax
$ echo '0x48 0x63 0xc0' | ./llvm-mc -disassemble -triple=x86_64 -x86-asm-syntax=intel
movsxd RAX, EAX

So yes, Intel is discouraging the 32-bit (no REX prefix) variant since it's a copy of another instruction, except in this case it would have a misleading mnemonic. AMD doesn't seem to care. I guess this is good enough.

[bcardosolopes]

mentioned in issue llvm/llvm-bugzilla-archive#10988