Unnecessary sign-extension for `LeadingZeroCount(UInt64)`

[xtqqczze]

public static class LeadingZeroCount {
    public static nint M1(ulong mask) {
        return BitOperations.LeadingZeroCount(mask);
    }
    
    public static nint M2(ulong mask) {
        return (nint)ulong.LeadingZeroCount(mask);
    }
}

public static class TrailingZeroCount {
    public static nint M1(ulong mask) {
        return BitOperations.TrailingZeroCount(mask);
    }
    
    public static nint M2(ulong mask) {
        return (nint)ulong.TrailingZeroCount(mask);
    }
}

public static class PopCount {
    public static nint M1(ulong mask) {
        return BitOperations.PopCount(mask);
    }
    
    public static nint M2(ulong mask) {
        return (nint)ulong.PopCount(mask);
    }
}

// coreclr trunk-20250917+116db00b333e27b70b6e97c93bcfb304ca4245ab

LeadingZeroCount:M1(ulong):nint (FullOpts):
       xor      eax, eax
       lzcnt    rax, rdi
       cdqe     
       ret      

LeadingZeroCount:M2(ulong):nint (FullOpts):
       xor      eax, eax
       lzcnt    rax, rdi
       ret      

TrailingZeroCount:M1(ulong):nint (FullOpts):
       xor      eax, eax
       tzcnt    rax, rdi
       cdqe     
       ret      

TrailingZeroCount:M2(ulong):nint (FullOpts):
       xor      eax, eax
       tzcnt    rax, rdi
       ret      

PopCount:M1(ulong):nint (FullOpts):
       xor      eax, eax
       popcnt   rax, rdi
       cdqe     
       ret      

PopCount:M2(ulong):nint (FullOpts):
       xor      eax, eax
       popcnt   rax, rdi
       ret             

godbolt.org

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[pinkfloydx33]

@xtqqczze FYI TrailingZeroCount.M2 in your example is calling LeadingZeroCount (I assume a typo)

[EgorBo]

Presumably should be trivial to fix, thanks for filing

[xtqqczze]

Confusingly the intrinsic is now named NI_AVX2_X64_LeadingZeroCount, despite LZCNT not being related to AVX2.

[tannergooding]

While the intrinsic isn't technically part of the AVX2 CPUID bit, it is logically part of the AVX2 family of instructions alongside BMI1, BMI2, F16C, and FMA. That is, the ISA bits were all introduced simultaneously and have not appeared in hardware independently. -- Formally, Intel defines POPCNT is part of SSE4.2 and LZCNT is part of BMI1, they exist as separate CPUID bits for compat with AMD which had them in their own earlier ABM instruction set.

The JIT took several simplifications last release to "merge" various logical ISA groupings together. This was done to significantly simplify the testing, support, and general codegen complexity matrices. Such logical groupings are always disabled or enabled together and this flows with the new "unified" versioning scheme that is intended to exist moving forward under AVX10.

In .NET 10, we have:

• CMOV+CX8+SSE+SSE2 - baseline, logically x86-64-v1
• SSE3+SSSE3+SSE4.1+SSE4.2+POPCNT - logically x86-64-v2
• AVX - kept because enough real world AVX only hardware existed, making it significant enough to support
• AVX2+BMI1+BMI2+F16C+FMA+LZCNT+MOVBE - logically x86-64-v3
• AVX512F+BW+CD+DQ+VL - logically x86-64-v4

We then define some "pseudo-versions" for AVX512v2 (IFMA+VBMI) and AVX512v3 (BITALG+VBMI2+VNNI+VPOPCNTDQ), which also represent the real world logical groupings. After that, we just have AVX10v1, AVX10v2, and will continue versioning this way in the future.

In .NET 11 we have raised the baseline to x86-64-v2 and so NI_SSE42_* no longer exists, it is simply part of NI_X86Base_*

[xtqqczze]

@tannergooding The naming here does feel a bit misleading, especially considering the existence of vector leading-zero count instructions.

[xtqqczze]

Look like the sign-extension for the M2 case was elided starting from .NET 8.

[tannergooding]

It's no different than other scalar vs vector form instructions that exist in a given ISA. We differentiate where important/relevant

We can always do so here in the future if it becomes important. For now, it was the change that allowed simplification of the JIT without also being a massively in depth refactoring