Remove Enable Signal from Generated HDL

[ThePerfectComputer]

I have the following haskell code which when lowered to Verilog, will leave the enable signal unconnected(using exposeEnable), but how can I eliminate it entirely from the netlist?

module Example.Blinky(topEntity, main) where
import Clash.Prelude

blinky :: HiddenClockResetEnable dom => Signal dom (BitVector 1)
blinky = register 0 (fmap toggle curr_state)
  where curr_state   = blinky
        toggle state = case state of
                         0 -> 1
                         1 -> 0
                         _ -> 0

sim_results = sampleN @System 4 blinky

topEntity ::
  HiddenClockResetEnable System => Signal System (BitVector 1)
topEntity =
  exposeEnable blinky enableGen

main :: IO ()
main = do
  putStrLn "Simulating Blinky"
  putStrLn $ show sim_results

[rowanG077]

Your TopEntity still has an unused enable as an input because it still has Hidden*Enable. Generally I don't use hidden arguments on the topEntity. So for you I would write it like this:

topEntity ::
  Clock System -> Reset System -> Signal System (BitVector 1)
topEntity clk rst = exposeClockResetEnable blinky clk rst enableGen

This should rid it of any enable signals.

[ThePerfectComputer]

Thanks! This feels more natural/idomatic for TopEntity.