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@Rot127 Rot127 commented Jun 25, 2025

Your checklist for this pull request

  • I've documented or updated the documentation of every API function and struct this PR changes.
  • I've added tests that prove my fix is effective or that my feature works (if possible)

Detailed description

Handles the edge case from the ISA when the R1 field of an instruction is 0.
In this case the R1 field is not ORed with the upper instruction bits.
In order to have unchanged instruction details even for this edge case, the instructions have now only a 0 immediate as neutral operand.

Test plan

added

Closing issues

closes #2741

@github-actions github-actions bot added the SystemZ Arch label Jun 25, 2025
@notxvilka
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@kabeor @jiegec please take a look at this one too

@Rot127 Rot127 merged commit 717d8b0 into capstone-engine:next Jul 8, 2025
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@Rot127 Rot127 deleted the systemz-exrl branch July 8, 2025 11:43
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s390x incorrect disassembly exrl inst since capstone 6.0.0a4

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