Skip to content

global code reformatting #41

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Feb 26, 2025
Merged

global code reformatting #41

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
a662808
tools: added reformatting style and script
tridge Dec 1, 2024
67ff553
global reformatting to match AM32 code style
tridge Feb 26, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
170 changes: 85 additions & 85 deletions Mcu/e230/Inc/blutil.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -25,27 +25,27 @@

static inline void gpio_mode_set_input(uint32_t pin, uint32_t pull_up_down)
{
gpio_mode_set(input_port, GPIO_MODE_INPUT, pull_up_down, pin);
gpio_mode_set(input_port, GPIO_MODE_INPUT, pull_up_down, pin);
}

static inline void gpio_mode_set_output(uint32_t pin, uint32_t output_mode)
{
gpio_mode_set(input_port, GPIO_MODE_OUTPUT, output_mode, pin);
gpio_mode_set(input_port, GPIO_MODE_OUTPUT, output_mode, pin);
}

static inline void gpio_set(uint32_t pin)
{
gpio_bit_set(input_port, pin);
gpio_bit_set(input_port, pin);
}

static inline void gpio_clear(uint32_t pin)
{
gpio_bit_reset(input_port, pin);
gpio_bit_reset(input_port, pin);
}

static inline bool gpio_read(uint32_t pin)
{
return (gpio_input_port_get(input_port) & pin) != 0;
return (gpio_input_port_get(input_port) & pin) != 0;
}

#define BL_TIMER TIMER16
Expand All @@ -55,33 +55,33 @@ static inline bool gpio_read(uint32_t pin)
*/
static inline void bl_timer_init(void)
{
rcu_periph_clock_enable(RCU_TIMER16);
TIMER_CAR(BL_TIMER) = 0xFFFF;
TIMER_PSC(BL_TIMER) = 71;
timer_auto_reload_shadow_enable(BL_TIMER);
timer_enable(BL_TIMER);
rcu_periph_clock_enable(RCU_TIMER16);
TIMER_CAR(BL_TIMER) = 0xFFFF;
TIMER_PSC(BL_TIMER) = 71;
timer_auto_reload_shadow_enable(BL_TIMER);
timer_enable(BL_TIMER);
}

/*
disable timer ready for app start
*/
static inline void bl_timer_disable(void)
{
timer_disable(BL_TIMER);
timer_disable(BL_TIMER);
}

static inline uint16_t bl_timer_us(void)
{
return timer_counter_read(BL_TIMER);
return timer_counter_read(BL_TIMER);
}

/*
initialise clocks
*/
static inline void bl_clock_config(void)
{
rcu_periph_clock_enable(RCU_GPIOA);
rcu_periph_clock_enable(RCU_GPIOB);
rcu_periph_clock_enable(RCU_GPIOA);
rcu_periph_clock_enable(RCU_GPIOB);
}

static inline void bl_gpio_init(void)
Expand All @@ -93,30 +93,30 @@ static inline void bl_gpio_init(void)
*/
static inline bool bl_was_software_reset(void)
{
return (RCU_RSTSCK & RCU_RSTSCK_SWRSTF) != 0;
return (RCU_RSTSCK & RCU_RSTSCK_SWRSTF) != 0;
}

/*
jump from the bootloader to the application code
*/
static inline void jump_to_application(void)
{
__disable_irq();
bl_timer_disable();
const uint32_t app_address = MCU_FLASH_START + FIRMWARE_RELATIVE_START;
const uint32_t *app_data = (const uint32_t *)app_address;
const uint32_t stack_top = app_data[0];
const uint32_t JumpAddress = app_data[1];
__disable_irq();
bl_timer_disable();
const uint32_t app_address = MCU_FLASH_START + FIRMWARE_RELATIVE_START;
const uint32_t *app_data = (const uint32_t *)app_address;
const uint32_t stack_top = app_data[0];
const uint32_t JumpAddress = app_data[1];

// setup vector table
SCB->VTOR = app_address;
// setup vector table
SCB->VTOR = app_address;

// setup sp, msp and jump
asm volatile(
"mov sp, %0 \n"
"msr msp, %0 \n"
"bx %1 \n"
: : "r"(stack_top), "r"(JumpAddress) :);
// setup sp, msp and jump
asm volatile(
"mov sp, %0 \n"
"msr msp, %0 \n"
"bx %1 \n"
: : "r"(stack_top), "r"(JumpAddress) :);
}

void SysTick_Handler(void)
Expand All @@ -138,51 +138,51 @@ void SysTick_Handler(void)

static void system_clock_72m_irc8m(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;

/* enable IRC8M */
RCU_CTL0 |= RCU_CTL0_IRC8MEN;
/* enable IRC8M */
RCU_CTL0 |= RCU_CTL0_IRC8MEN;

/* wait until IRC8M is stable or the startup time is longer than
* IRC8M_STARTUP_TIMEOUT */
do {
timeout++;
stab_flag = (RCU_CTL0 & RCU_CTL0_IRC8MSTB);
} while ((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
/* wait until IRC8M is stable or the startup time is longer than
* IRC8M_STARTUP_TIMEOUT */
do {
timeout++;
stab_flag = (RCU_CTL0 & RCU_CTL0_IRC8MSTB);
} while ((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));

/* if fail */
if (0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)) {
while (1) {
}
/* if fail */
if (0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)) {
while (1) {
}
}

FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT_2;
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT_2;

/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB2 = AHB */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
/* PLL = (IRC8M/2) * 18 = 72 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18);
/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB2 = AHB */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
/* PLL = (IRC8M/2) * 18 = 72 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18);

/* enable PLL */
RCU_CTL0 |= RCU_CTL0_PLLEN;
/* enable PLL */
RCU_CTL0 |= RCU_CTL0_PLLEN;

/* wait until PLL is stable */
while (0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)) {
}
/* wait until PLL is stable */
while (0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)) {
}

/* select PLL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
/* select PLL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL;

/* wait until PLL is selected as system clock */
while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) {
}
/* wait until PLL is selected as system clock */
while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) {
}
}

/*!
Expand All @@ -193,7 +193,7 @@ static void system_clock_72m_irc8m(void)
*/
static void system_clock_config(void)
{
system_clock_72m_irc8m();
system_clock_72m_irc8m();
}

/*!
Expand All @@ -204,24 +204,24 @@ static void system_clock_config(void)
*/
void SystemInit(void)
{
/* enable IRC8M */
RCU_CTL0 |= RCU_CTL0_IRC8MEN;
while (0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)) {
}

RCU_MODIFY(0x80);
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
/* reset RCU */
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
RCU_CFG1 &= ~(RCU_CFG1_PREDV);
RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL);
RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
RCU_CFG2 &= ~RCU_CFG2_ADCPSC2;
RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
RCU_INT = 0x00000000U;

/* configure system clock */
system_clock_config();
/* enable IRC8M */
RCU_CTL0 |= RCU_CTL0_IRC8MEN;
while (0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)) {
}

RCU_MODIFY(0x80);
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
/* reset RCU */
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
RCU_CFG1 &= ~(RCU_CFG1_PREDV);
RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL);
RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
RCU_CFG2 &= ~RCU_CFG2_ADCPSC2;
RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
RCU_INT = 0x00000000U;

/* configure system clock */
system_clock_config();
}
54 changes: 27 additions & 27 deletions Mcu/e230/Src/eeprom.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,35 +8,35 @@

bool save_flash_nolib(const uint8_t* data, uint32_t length, uint32_t add)
{
if ((add & 0x3) != 0 || (length & 0x3) != 0) {
return false;
}
const uint32_t data_length = length / 4;

// unlock flash

fmc_unlock();

// erase page if address even divisable by 1024
if ((add % page_size) == 0) {
fmc_page_erase(add);
}

volatile uint32_t index = 0;
while (index < data_length) {
uint32_t word;
memcpy(&word, (void*)(data+(index*4)), sizeof(word));
fmc_word_program(add + (index * 4), word);
fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_WPERR | FMC_FLAG_PGERR);
index++;
}
fmc_lock();

// ensure data is correct
return memcmp(data, (const void *)add, length) == 0;
if ((add & 0x3) != 0 || (length & 0x3) != 0) {
return false;
}
const uint32_t data_length = length / 4;

// unlock flash

fmc_unlock();

// erase page if address even divisable by 1024
if ((add % page_size) == 0) {
fmc_page_erase(add);
}

volatile uint32_t index = 0;
while (index < data_length) {
uint32_t word;
memcpy(&word, (void*)(data+(index*4)), sizeof(word));
fmc_word_program(add + (index * 4), word);
fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_WPERR | FMC_FLAG_PGERR);
index++;
}
fmc_lock();

// ensure data is correct
return memcmp(data, (const void *)add, length) == 0;
}

void read_flash_bin(uint8_t* data, uint32_t add, int out_buff_len)
{
memcpy(data, (void*)add, out_buff_len);
memcpy(data, (void*)add, out_buff_len);
}
Loading