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STM32H7: enable QSPI #12677

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Merged
merged 1 commit into from
Mar 27, 2020
Merged

STM32H7: enable QSPI #12677

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8 changes: 8 additions & 0 deletions targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h
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Original file line number Diff line number Diff line change
Expand Up @@ -428,6 +428,14 @@ typedef enum {
ETH_TX_EN = PG_11,
ETH_TX_EN_ALT0 = PB_11,

/**** QSPI FLASH pins ****/
QSPI_FLASH1_IO0 = PD_11,
QSPI_FLASH1_IO1 = PF_9,
QSPI_FLASH1_IO2 = PF_7,
QSPI_FLASH1_IO3 = PF_6,
QSPI_FLASH1_SCK = PB_2,
QSPI_FLASH1_CSN = PG_6,

/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
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13 changes: 13 additions & 0 deletions targets/TARGET_STM/TARGET_STM32H7/objects.h
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Original file line number Diff line number Diff line change
Expand Up @@ -146,6 +146,19 @@ struct analogin_s {
uint8_t differential;
};

#if DEVICE_QSPI
struct qspi_s {
QSPI_HandleTypeDef handle;
QSPIName qspi;
PinName io0;
PinName io1;
PinName io2;
PinName io3;
PinName sclk;
PinName ssel;
};
#endif

#define GPIO_IP_WITHOUT_BRR

#if defined(DUAL_CORE)
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10 changes: 8 additions & 2 deletions targets/targets.json
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Original file line number Diff line number Diff line change
Expand Up @@ -4905,6 +4905,7 @@
],
"core": "Cortex-M7FD",
"components_add": [
"QSPIF",
"FLASHIAP"
],
"mbed_rom_start": "0x08000000",
Expand All @@ -4914,7 +4915,8 @@
"extra_labels_add": [
"STM32H7",
"STM32H747xI",
"DISCO_H747I_CM7"
"DISCO_H747I_CM7",
"MT25QL512"
],
"config": {
"clock_source": {
Expand Down Expand Up @@ -4950,6 +4952,7 @@
"CRC",
"TRNG",
"FLASH",
"QSPI",
"MPU"
],
"release_versions": [
Expand All @@ -4967,9 +4970,11 @@
"extra_labels_add": [
"STM32H7",
"STM32H747xI",
"DISCO_H747I"
"DISCO_H747I",
"MT25QL512"
],
"components_add": [
"QSPIF",
"FLASHIAP"
],
"mbed_rom_start": "0x08100000",
Expand Down Expand Up @@ -5007,6 +5012,7 @@
"CRC",
"TRNG",
"FLASH",
"QSPI",
"MPU"
],
"bootloader_supported": true
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