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Update CM0P pre-built images to build 1.0.0.35 #11770

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95 changes: 95 additions & 0 deletions targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_BLESS/README.md
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# PSoC 6 Cortex M0+ BLESS Controller pre-built image (CM0P_BLESS)

### Overview
Pre-compiled BLESS Controller image executed on the Cortex M0+ core of the PSoC 6 dual-core MCU.
The image is provided as C array ready to be compiled as part of the Cortex M4 application.
The Cortex M0+ application code is placed to internal flash by the Cortex M4 linker script.

This image is used only in BLE dual CPU mode. In this mode, the BLE functionality is split between
CM0+ (controller) and CM4 (host). It uses IPC for communication between two CPU cores where both the
controller and host run:

------------------------------- ------------------------------------
| CM0p (pre-built image) | | CM4 |
| -------------------- ----- | | ----- ------------------------ |
| | | | H | | IPC | | | | BLE Application | |
| | BLE Controller |--| c | |<-------->| | | ------------------------ |
| | (LL) | | I | |(commands,| | | | | |
| | | ----- | events) | | | ----------------- | |
| -------------------- | | | H | | BLE Profiles | | |
------------------------------- | | C | ----------------- | |
| | | I | | | |
------------------------ | | | ------------------------- |
| BLE HW | | | |--| BLE Host (GAP, L2CAP,| |
------------------------ | | | | SM, ATT) | |
| | | ------------------------- |
| ----- |
------------------------------------


BLESS Controller pre-built image executes the following steps:
- configures BLESS interrupt
- registers IPC-pipe callback for BLE middleware; the BLE middleware uses this callback to
initialize and enable the BLE controller when BLE middleware operates in BLE dual CPU mode
- starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x10020000
- goes to the while loop where processes BLE controller events and puts the CM0+ core into Deep Sleep.

### Usage
To use this image, update the ram, flash, and FLASH_CM0P_SIZE values in the linker script for CM4:
```
Example for the GCC compiler:
...
MEMORY
{
...
ram (rwx) : ORIGIN = 0x08003000, LENGTH = 0x044800
flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000
...
}
...
/* The size and start addresses of the Cortex-M0+ application image */
FLASH_CM0P_SIZE = 0x20000;
...
```
```
Example for the IAR compiler:
...
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = 0x08003000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
...
/* The size and start addresses of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x20000;
...
```
```
Example for ARMC6 compiler:
...
; RAM
#define RAM_START 0x08003000
#define RAM_SIZE 0x00044800
; Flash
#define FLASH_START 0x10000000
#define FLASH_SIZE 0x00100000
...
/* The size and start addresses of the Cortex-M0+ application image */
#define FLASH_CM0P_SIZE 0x20000
...
```

To use this image in the custom BSP, adjust the BSP target makefile to
add the COMPONENT_CM0P_BLESS directory to the list of components
discovered by ModusToolbox build system:

```
COMPONENTS+=CM0P_BLESS
```

Make sure there is a single CM0P_* component included in the COMPONENTS list
(it might be needed to remove CM0P_SLEEP from the list of standard BSP components).

---
Copyright (c) Cypress Semiconductor Corporation, 2019.
6,763 changes: 6,763 additions & 0 deletions targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_BLESS/psoc6_cm0p_bless.c
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91 changes: 91 additions & 0 deletions targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/README.md
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# PSoC 6 Cortex M0+ Crypto server prebuilt image (CM0P_CRYPTO)

### Overview
Crypto server prebuilt application image is executed on the Cortex M0+ core of the PSoC 6 dual-core MCU.
The image is provided as C array ready to be compiled as part of the Cortex M4 application.
The Cortex M0+ application code is placed to internal flash by the Cortex M4 linker script.

The Crypto server image executes the following steps:
- configures IPC channel for data exchange between client and server applications;
- configures three interrupts: an IPC notify interrupt, an IPC release interrupt, and an interrupt for error handling.
- starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x10008000
- goes to the infinite loop that processes the crypto server events and puts the CM0+ core into Deep Sleep.

### Usage
To use this image, update the FLASH_CM0P_SIZE value in the linker script for CM4:
```
Example for the GCC compiler:
...
/* The size and start addresses of the Cortex-M0+ application image */
FLASH_CM0P_SIZE = 0x8000;
...
```
```
Example for the IAR compiler:
...
/* The size and start addresses of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x8000;
...
```
```
Example for ARMC6 compiler:
...
/* The size and start addresses of the Cortex-M0+ application image */
#define FLASH_CM0P_SIZE 0x8000
...
```

To use this image in the custom BSP, adjust the BSP target makefile to
add the COMPONENT_CM0P_CRYPTO directory to the list of components
discovered by ModusToolbox build system:

```
COMPONENTS+=CM0P_CRYPTO
```

Make sure there is a single CM0P_* component included in the COMPONENTS list
(it might be needed to remove CM0P_SLEEP from the list of standard BSP components).


### Crypto client configuration

Example configuration of the crypto client for the Cortex-M4 core
compatible with the prebuilt crypto server CM0+ application:

```
#define MY_CHAN_CRYPTO (uint32_t)(3u) /* IPC data channel for the Crypto */
#define MY_INTR_CRYPTO_SRV (uint32_t)(1u) /* IPC interrupt structure for the Crypto server */
#define MY_INTR_CRYPTO_CLI (uint32_t)(2u) /* IPC interrupt structure for the Crypto client */
#define MY_INTR_CRYPTO_SRV_MUX (IRQn_Type)(2u) /* CM0+ IPC interrupt mux number the Crypto server */
#define MY_INTR_CRYPTO_CLI_MUX (IRQn_Type)(3u) /* CM0+ IPC interrupt mux number the Crypto client */
#define MY_INTR_CRYPTO_ERR_MUX (IRQn_Type)(4u) /* CM0+ ERROR interrupt mux number the Crypto server */

const cy_stc_crypto_config_t myCryptoConfig =
{
/* .ipcChannel */ MY_CHAN_CRYPTO,
/* .acquireNotifierChannel */ MY_INTR_CRYPTO_SRV,
/* .releaseNotifierChannel */ MY_INTR_CRYPTO_CLI,
/* .releaseNotifierConfig */ {
/* .cm0pSrc */ cpuss_interrupts_ipc_2_IRQn, /* depends on selected releaseNotifierChannel value */
/* .intrPriority */ 2u,
},
/* .userCompleteCallback */ NULL,
/* .userGetDataHandler */ NULL,
/* .userErrorHandler */ NULL,
/* .acquireNotifierConfig */ {
/* .cm0pSrc */ cpuss_interrupts_ipc_1_IRQn, /* depends on selected acquireNotifierChannel value */
/* .intrPriority */ 2u,
},
/* .cryptoErrorIntrConfig */ {
/* .cm0pSrc */ cpuss_interrupt_crypto_IRQn,
/* .intrPriority */ 2u,
}
};
```

Refer to the [PDL API Reference Guide][pdl_crypto] for more information related to the PSoC 6 Crypto client configuration.

---
Copyright (c) Cypress Semiconductor Corporation, 2019.

[pdl_crypto]: https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__crypto__cli__srv.html
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