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Merged
merged 4 commits into from
Oct 16, 2019
Merged

DISCO_H747I dualcore support #11605

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adcf0e2
DISCO_H747I Dualcore support
ABOSTM Oct 14, 2019
48aba33
SystemCoreClock should correspond to current core clock and not D1 cl…
ABOSTM Sep 30, 2019
02cdac5
Update HAL/LL EXTI to have default API applied on current core and no…
ABOSTM Sep 30, 2019
6397a1d
Mbed patch of STM32cube for bootloader: use NVIC_FLASH_VECTOR_ADDRESS
ABOSTM Sep 27, 2019
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8 changes: 8 additions & 0 deletions features/mbedtls/targets/TARGET_STM/aes_alt.c
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Original file line number Diff line number Diff line change
Expand Up @@ -103,11 +103,19 @@ void mbedtls_aes_free(mbedtls_aes_context *ctx)
if (ctx == NULL) {
return;
}
#if defined(DUAL_CORE)
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@bulislaw bulislaw Oct 1, 2019

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@Patater please review

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@ABOSTM ABOSTM Oct 1, 2019

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You are right this is up to the user to put whatever on both cores, and to figure out how they could talk to each other.
The modification in this specific file aes_alt.c concerns the potential concurent access (by CM4 and CM7) to common resource (RCC registers). This is done through Hardware Semaphore.

uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
}
#endif /* DUAL_CORE */
/* Force the CRYP Periheral Clock Reset */
__HAL_RCC_CRYP_FORCE_RESET();

/* Release the CRYP Periheral Clock Reset */
__HAL_RCC_CRYP_RELEASE_RESET();
#if defined(DUAL_CORE)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */

mbedtls_zeroize(ctx, sizeof(mbedtls_aes_context));
}
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16 changes: 8 additions & 8 deletions targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c
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Expand Up @@ -198,14 +198,14 @@ MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
// You have to comment all PWM using TIM_MST defined in hal_tick.h file
// or update python script (check TIM_MST_LIST) and re-run it
MBED_WEAK const PinMap PinMap_PWM[] = {
{PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to PMOD\#1- USART2_CTS_NSS
{PA_0_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to PMOD\#1- USART2_CTS_NSS
{PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to ETH_REF_CLK
{PA_1_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to ETH_REF_CLK
{PA_1_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N // Connected to ETH_REF_CLK
{PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to ETH_MDIO
{PA_2_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to ETH_MDIO
{PA_2_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 // Connected to ETH_MDIO
// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to PMOD\#1- USART2_CTS_NSS
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@bulislaw bulislaw Oct 1, 2019

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Dead code.

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@jeromecoutant jeromecoutant Oct 1, 2019

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Yes and no...
We used to keep all the lines in all targets .
As the PinMap table is weak, idea was to give the availability for customer to change easily the default choice.

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@ABOSTM ABOSTM Oct 1, 2019

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From pin configuration point of view, PA_0 can be connected to TIM2_CH1.
Nevertheless TIM2 and TIM5 are reserved for us_ticker.
That is why thoses lines are commented out: it is nomore usable for PWM purpose.
but we keep those lines as reminder to show the capability.
It is done the same way for example on target NUCLEO_L4R5ZI_P.

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@bulislaw bulislaw Oct 4, 2019

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Makes sense.

// {PA_0_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to PMOD\#1- USART2_CTS_NSS
// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to ETH_REF_CLK
// {PA_1_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to ETH_REF_CLK
{PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N // Connected to ETH_REF_CLK
// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to ETH_MDIO
// {PA_2_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to ETH_MDIO
{PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 // Connected to ETH_MDIO
{PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to ULPI_D0
{PA_3_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to ULPI_D0
{PA_3_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 // Connected to ULPI_D0
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46 changes: 27 additions & 19 deletions targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_stm32h7xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -17,8 +17,8 @@
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* - SystemCoreClockUpdate(): Updates the variables SystemD1Clock and SystemD2Clock
* and must be called whenever the core clock is changed
* during program execution.
*
*
Expand Down Expand Up @@ -50,6 +50,7 @@

#include "stm32h7xx.h"
#include <math.h>
#include "nvic_addr.h" // MBED PATCH for Bootloader

#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
Expand Down Expand Up @@ -111,7 +112,14 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 64000000;
#if defined(CORE_CM7)
#define SystemCoreClock SystemD1Clock
#elif defined(CORE_CM4)
#define SystemCoreClock SystemD2Clock
#else
#error "Wrong core selection"
#endif
uint32_t SystemD1Clock = 64000000;
uint32_t SystemD2Clock = 64000000;
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};

Expand Down Expand Up @@ -216,7 +224,7 @@ void SystemInit (void)
#ifdef VECT_TAB_SRAM
SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ // MBED PATCH for Bootloader
#endif

#else
Expand All @@ -226,7 +234,7 @@ void SystemInit (void)
#ifdef VECT_TAB_SRAM
SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM */
#else
SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ // MBED PATCH for Bootloader
#endif

#else
Expand All @@ -237,7 +245,7 @@ void SystemInit (void)
}

/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* @brief Update SystemD1Clock and SystemD2Clock variables according to Clock Register Values.
* The SystemCoreClock variable contains the core clock , it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
Expand All @@ -250,10 +258,10 @@ void SystemInit (void)
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
* - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
* - If SYSCLK source is CSI, SystemD1Clock will contain the CSI_VALUE(*)
* - If SYSCLK source is HSI, SystemD1Clock will contain the HSI_VALUE(**)
* - If SYSCLK source is HSE, SystemD1Clock will contain the HSE_VALUE(***)
* - If SYSCLK source is PLL, SystemD1Clock will contain the CSI_VALUE(*),
* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
*
* (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
Expand Down Expand Up @@ -283,16 +291,16 @@ void SystemCoreClockUpdate (void)
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
SystemD1Clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));

break;

case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
SystemCoreClock = CSI_VALUE;
SystemD1Clock = CSI_VALUE;
break;

case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
SystemD1Clock = HSE_VALUE;
break;

case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
Expand Down Expand Up @@ -329,27 +337,27 @@ void SystemCoreClockUpdate (void)
break;
}
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
SystemD1Clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
}
else
{
SystemCoreClock = 0U;
SystemD1Clock = 0U;
}
break;

default:
SystemCoreClock = CSI_VALUE;
SystemD1Clock = CSI_VALUE;
break;
}

/* Compute SystemClock frequency --------------------------------------------------*/
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];

/* SystemCoreClock frequency : CM7 CPU frequency */
SystemCoreClock >>= tmp;
/* SystemD1Clock frequency : CM7 CPU frequency */
SystemD1Clock >>= tmp;

/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
SystemD2Clock = (SystemD1Clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));

}

Expand Down
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