Add target for CY8CKIT_062S2_43012

features/lwipstack/mbed_lib.json

@@ -217,6 +217,20 @@
             "pbuf-pool-size": 48,
             "mem-size": 65536
         },
+        "CY8CKIT_062S2_43012": {
+           "tcpip-thread-stacksize": 8192,
+           "default-thread-stacksize": 640,
+           "ppp-thread-stacksize": 896,
+           "memp-num-tcp-seg": 24,
+           "tcp-socket-max": 10,
+           "udp-socket-max":10,
+           "socket-max":18,
+           "tcp-mss": 1540,
+           "tcp-snd-buf": "(6 * TCP_MSS)",
+           "tcp-wnd": "(TCP_MSS * 6)",
+           "pbuf-pool-size": 96,
+           "mem-size": 92610
+        },
         "MIMXRT1050_EVK": {
             "mem-size": 36560
         },

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg.c

@@ -0,0 +1,34 @@
+/*******************************************************************************
+* File Name: cycfg.c
+*
+* Description:
+* Wrapper function to initialize all generated code.
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg.h"
+
+void init_cycfg_all(void)
+{
+	init_cycfg_system();
+	init_cycfg_clocks();
+	init_cycfg_routing();
+	init_cycfg_peripherals();
+	init_cycfg_pins();
+}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg.h

@@ -0,0 +1,47 @@
+/*******************************************************************************
+* File Name: cycfg.h
+*
+* Description:
+* Simple wrapper header containing all generated files.
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_H)
+#define CYCFG_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_notices.h"
+#include "cycfg_system.h"
+#include "cycfg_clocks.h"
+#include "cycfg_routing.h"
+#include "cycfg_peripherals.h"
+#include "cycfg_pins.h"
+
+void init_cycfg_all(void);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_clocks.c

@@ -0,0 +1,45 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.c
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_clocks.h"
+
+
+void init_cycfg_clocks(void)
+{
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 51U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1U, 77U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 5U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_clocks.h

@@ -0,0 +1,55 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.h
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_CLOCKS_H)
+#define CYCFG_CLOCKS_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
+#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
+#define CYBSP_DEBUG_UART_CLK_DIV_NUM 0U
+#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
+#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
+#define CYBSP_BT_UART_CLK_DIV_NUM 1U
+#define CYBSP_CSD_CLK_DIV_ENABLED 1U
+#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CSD_CLK_DIV_NUM 0U
+#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
+#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
+
+void init_cycfg_clocks(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_CLOCKS_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_notices.h

@@ -0,0 +1,30 @@
+/*******************************************************************************
+* File Name: cycfg_notices.h
+*
+* Description:
+* Contains warnings and errors that occurred while generating code for the
+* design.
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_NOTICES_H)
+#define CYCFG_NOTICES_H
+
+
+#endif /* CYCFG_NOTICES_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_peripherals.c

@@ -0,0 +1,155 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.c
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_peripherals.h"
+
+cy_stc_csd_context_t cy_csd_0_context = 
+{
+	.lockKey = CY_CSD_NONE_KEY,
+};
+const cy_stc_scb_uart_config_t CYBSP_BT_UART_config = 
+{
+	.uartMode = CY_SCB_UART_STANDARD,
+	.enableMutliProcessorMode = false,
+	.smartCardRetryOnNack = false,
+	.irdaInvertRx = false,
+	.irdaEnableLowPowerReceiver = false,
+	.oversample = 8,
+	.enableMsbFirst = false,
+	.dataWidth = 8UL,
+	.parity = CY_SCB_UART_PARITY_NONE,
+	.stopBits = CY_SCB_UART_STOP_BITS_1,
+	.enableInputFilter = false,
+	.breakWidth = 11UL,
+	.dropOnFrameError = false,
+	.dropOnParityError = false,
+	.receiverAddress = 0x0UL,
+	.receiverAddressMask = 0x0UL,
+	.acceptAddrInFifo = false,
+	.enableCts = true,
+	.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
+	.rtsRxFifoLevel = 63,
+	.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
+	.rxFifoTriggerLevel = 1UL,
+	.rxFifoIntEnableMask = 0UL,
+	.txFifoTriggerLevel = 63UL,
+	.txFifoIntEnableMask = 0UL,
+};
+const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config = 
+{
+	.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
+	.slaveAddress1 = 8U,
+	.slaveAddress2 = 0U,
+	.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
+	.enableWakeFromSleep = false,
+};
+const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config = 
+{
+	.uartMode = CY_SCB_UART_STANDARD,
+	.enableMutliProcessorMode = false,
+	.smartCardRetryOnNack = false,
+	.irdaInvertRx = false,
+	.irdaEnableLowPowerReceiver = false,
+	.oversample = 12,
+	.enableMsbFirst = false,
+	.dataWidth = 9UL,
+	.parity = CY_SCB_UART_PARITY_NONE,
+	.stopBits = CY_SCB_UART_STOP_BITS_1,
+	.enableInputFilter = false,
+	.breakWidth = 11UL,
+	.dropOnFrameError = false,
+	.dropOnParityError = false,
+	.receiverAddress = 0x0UL,
+	.receiverAddressMask = 0x0UL,
+	.acceptAddrInFifo = false,
+	.enableCts = true,
+	.ctsPolarity = CY_SCB_UART_ACTIVE_HIGH,
+	.rtsRxFifoLevel = 63,
+	.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
+	.rxFifoTriggerLevel = 63UL,
+	.rxFifoIntEnableMask = 0UL,
+	.txFifoTriggerLevel = 63UL,
+	.txFifoIntEnableMask = 0UL,
+};
+cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity = CY_SD_HOST_SDSC;
+cy_en_sd_host_card_type_t CYBSP_RADIO_cardType = CY_SD_HOST_NOT_EMMC;
+uint32_t CYBSP_RADIO_rca = 0u;
+const cy_stc_sd_host_init_config_t CYBSP_RADIO_config = 
+{
+	.emmc = false,
+	.dmaType = CY_SD_HOST_DMA_SDMA,
+	.enableLedControl = false,
+};
+cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg = 
+{
+	.lowVoltageSignaling = false,
+	.busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT,
+	.cardType = &CYBSP_RADIO_cardType,
+	.rca = &CYBSP_RADIO_rca,
+	.cardCapacity = &CYBSP_RADIO_cardCapacity,
+};
+const cy_stc_smif_config_t CYBSP_QSPI_config = 
+{
+	.mode = (uint32_t)CY_SMIF_NORMAL,
+	.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
+	.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
+	.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
+};
+const cy_stc_mcwdt_config_t CYBSP_MCWDT_config = 
+{
+	.c0Match = 32768U,
+	.c1Match = 32768U,
+	.c0Mode = CY_MCWDT_MODE_NONE,
+	.c1Mode = CY_MCWDT_MODE_NONE,
+	.c2ToggleBit = 16U,
+	.c2Mode = CY_MCWDT_MODE_NONE,
+	.c0ClearOnMatch = false,
+	.c1ClearOnMatch = false,
+	.c0c1Cascade = true,
+	.c1c2Cascade = false,
+};
+const cy_stc_rtc_config_t CYBSP_RTC_config = 
+{
+	.sec = 0U,
+	.min = 0U,
+	.hour = 12U,
+	.amPm = CY_RTC_AM,
+	.hrFormat = CY_RTC_24_HOURS,
+	.dayOfWeek = CY_RTC_SUNDAY,
+	.date = 1U,
+	.month = CY_RTC_JANUARY,
+	.year = 0U,
+};
+
+
+void init_cycfg_peripherals(void)
+{
+	Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
+
+	Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_16_BIT, 1U);
+
+	Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
+
+	Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_16_BIT, 0U);
+}