Skip to content

FPGA shield uart test #11277

@wajahat-abbas

Description

@wajahat-abbas

Description

The FPGA uart test case "9600, 8O1, FC on" enables the odd parity and then checks if data sent by tester is received correctly by DUT uart. This test passes for K64F however it is failing for Ublox C030 targets.
The C030 boards use STM32F4 as MCU and according to the reference manual of this MCU, when parity is enabled, the MSB of value read from Data Register includes the parity bit. So in case of this MCU, the test case should mask the value read with 0xFF before doing the comparison.

Please consider this example:
Tester wrote 0x04 on uart.
Value read from DR is 0x04, the comparison succeeds because in this case the parity bit is set to 0 as parity of data byte is already odd.

Now the written value is incremented:
Tester writes 0x05.
Value read from DR is 0x105, the test asserts here as 0x05 != 0x105 however this is happening because the value in DR includes the parity bit which is now set to 1 as parity of data byte is not odd.

I would also like to know if this behavior is observed for any other targets with ST MCU. I tried on Nucleo-F429ZI but it seems the Arduino header does not have CTS/RTS pins so this test passes with following message:
[1566299117.84][CONN][RXD] Could not find pins for UART testing

@RobMeades @MarceloSalazar @fahim-ublox @c1728p9

Issue request type

[ ] Question
[ ] Enhancement
[X] Bug

Metadata

Metadata

Assignees

No one assigned

    Type

    No type

    Projects

    No projects

    Milestone

    No milestone

    Relationships

    None yet

    Development

    No branches or pull requests

    Issue actions