JIT/AArch64: Support shifted immediate

As pointed out by MikePall in [1], shifted immediate value is supported.
See [2]. For example, `add x0, x1, php#4096` would be encoded by DynASM
into `add x0, x1, php#1, lsl php#12` directly.

In this patch, a helper is added to check whether an immediate value is
in the two allowed ranges: (1) 0 to 4095, and (2) LSL php#12 on all the
values from the first range.

Note that this helper works for add/adds/sub/subs/cmp/cmn instructions.

[1] LuaJIT/LuaJIT#718
[2]
https://github.com/LuaJIT/LuaJIT/blob/v2.1/dynasm/dasm_arm64.lua#L342

Change-Id: I4870048b9b8e6c429b73a4803af2a3b2d5ec0fbb

Author: shqking

ext/opcache/jit/zend_jit_arm64.dasc

@@ -122,7 +122,7 @@ typedef struct TLVDescriptor TLVDescriptor;
 
 #define IS_SIGNED_32BIT(val) ((((intptr_t)(val)) <= 0x7fffffff) && (((intptr_t)(val)) >= (-2147483647 - 1)))
 
-/* Encoding of immediate. TODO: shift mode may be supported in the near future. */
+/* Encoding of immediate. */
 #define MAX_IMM12       0xfff          // maximum value for imm12
 #define MAX_IMM16       0xffff         // maximum value for imm16
 #define CMP_IMM         MAX_IMM12      // cmp insn
@@ -172,6 +172,11 @@ static bool arm64_may_use_adrp(const void *addr)
 	return 0;
 }
 
+static bool arm64_may_encode_imm12(const int64_t val)
+{
+	return (val >= 0 && (val < (1<<12) || !(val & 0xffffffffff000fff)));
+}
+
 /* Determine whether an immediate value can be encoded as the immediate operand of logical instructions. */
 static bool logical_immediate_p(uint64_t value, uint32_t reg_size)
 {
@@ -364,9 +369,9 @@ static bool logical_immediate_p(uint64_t value, uint32_t reg_size)
 |.macro CMP_32_WITH_CONST, reg, val, tmp_reg
 ||	if (val == 0) {
 |		cmp reg, wzr
-||	} else if (((int32_t)(val)) > 0 && ((int32_t)(val)) <= CMP_IMM) {
+||	} else if (arm64_may_encode_imm12((int64_t)(val))) {
 |		cmp reg, #val
-||	} else if (((int32_t)(val)) < 0 && ((int32_t)(val)) >= -CMP_IMM) {
+||	} else if (arm64_may_encode_imm12((int64_t)(-val))) {
 |		cmn reg, #-val
 ||	} else {
 |		LOAD_32BIT_VAL tmp_reg, val
@@ -377,9 +382,9 @@ static bool logical_immediate_p(uint64_t value, uint32_t reg_size)
 |.macro CMP_64_WITH_CONST_32, reg, val, tmp_reg
 ||	if (val == 0) {
 |		cmp reg, xzr
-||	} else if (((int32_t)(val)) > 0 && ((int32_t)(val)) <= CMP_IMM) {
+||	} else if (arm64_may_encode_imm12((int64_t)(val))) {
 |		cmp reg, #val
-||	} else if (((int32_t)(val)) < 0 && ((int32_t)(val)) >= -CMP_IMM) {
+||	} else if (arm64_may_encode_imm12((int64_t)(-val))) {
 |		cmn reg, #-val
 ||	} else {
 |		LOAD_32BIT_VAL tmp_reg, val
@@ -390,9 +395,9 @@ static bool logical_immediate_p(uint64_t value, uint32_t reg_size)
 |.macro CMP_64_WITH_CONST, reg, val, tmp_reg
 ||	if (val == 0) {
 |		cmp reg, xzr
-||	} else if (((int64_t)(val)) > 0 && ((int64_t)(val)) <= CMP_IMM) {
+||	} else if (arm64_may_encode_imm12((int64_t)(val))) {
 |		cmp reg, #val
-||	} else if (((int64_t)(val)) < 0 && ((int64_t)(val)) >= -CMP_IMM) {
+||	} else if (arm64_may_encode_imm12((int64_t)(-val))) {
 |		cmn reg, #-val
 ||	} else {
 |		LOAD_64BIT_VAL tmp_reg, val
@@ -406,7 +411,7 @@ static bool logical_immediate_p(uint64_t value, uint32_t reg_size)
 |.macro ADD_SUB_32_WITH_CONST, add_sub_ins, dst_reg, src_reg1, val, tmp_reg
 ||	if (val == 0) {
 |		add_sub_ins dst_reg, src_reg1, wzr
-||	} else if (((int32_t)(val)) > 0 && ((int32_t)(val)) <= ADD_SUB_IMM) {
+||	} else if (arm64_may_encode_imm12((int64_t)(val))) {
 |		add_sub_ins dst_reg, src_reg1, #val
 ||	} else {
 |		LOAD_32BIT_VAL tmp_reg, val
@@ -417,7 +422,7 @@ static bool logical_immediate_p(uint64_t value, uint32_t reg_size)
 |.macro ADD_SUB_64_WITH_CONST_32, add_sub_ins, dst_reg, src_reg1, val, tmp_reg
 ||	if (val == 0) {
 |		add_sub_ins dst_reg, src_reg1, xzr
-||	} else if (((int32_t)(val)) > 0 && ((int32_t)(val)) <= ADD_SUB_IMM) {
+||	} else if (arm64_may_encode_imm12((int64_t)(val))) {
 |		add_sub_ins dst_reg, src_reg1, #val
 ||	} else {
 |		LOAD_32BIT_VAL tmp_reg, val
@@ -428,7 +433,7 @@ static bool logical_immediate_p(uint64_t value, uint32_t reg_size)
 |.macro ADD_SUB_64_WITH_CONST, add_sub_ins, dst_reg, src_reg1, val, tmp_reg
 ||	if (val == 0) {
 |		add_sub_ins dst_reg, src_reg1, xzr
-||	} else if (((int64_t)(val)) > 0 && ((int64_t)(val)) <= ADD_SUB_IMM) {
+||	} else if (arm64_may_encode_imm12((int64_t)(val))) {
 |		add_sub_ins dst_reg, src_reg1, #val
 ||	} else {
 |		LOAD_64BIT_VAL tmp_reg, val