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tgross35tgross35
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Add f16 and f128 intrinsics to HIR
1 parent b880d90 commit e4816c3

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2 files changed

+78
-1
lines changed

2 files changed

+78
-1
lines changed

‎compiler/rustc_hir/src/hir.rs‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2460,6 +2460,7 @@ impl PrimTy {
24602460
Self::Uint(UintTy::Usize),
24612461
Self::Float(FloatTy::F32),
24622462
Self::Float(FloatTy::F64),
2463+
// FIXME(f16_f128): add these when enabled below
24632464
Self::Bool,
24642465
Self::Char,
24652466
Self::Str,
@@ -2509,6 +2510,10 @@ impl PrimTy {
25092510
sym::usize => Self::Uint(UintTy::Usize),
25102511
sym::f32 => Self::Float(FloatTy::F32),
25112512
sym::f64 => Self::Float(FloatTy::F64),
2513+
// FIXME(f16_f128): enabling these will open the gates of f16 and f128 being
2514+
// understood by rustc.
2515+
// sym::f16 => Self::Float(FloatTy::F16),
2516+
// sym::f128 => Self::Float(FloatTy::F128),
25122517
sym::bool => Self::Bool,
25132518
sym::char => Self::Char,
25142519
sym::str => Self::Str,

‎compiler/rustc_hir_analysis/src/check/intrinsic.rs‎

Lines changed: 73 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -112,11 +112,15 @@ pub fn intrinsic_operation_unsafety(tcx: TyCtxt<'_>, intrinsic_id: LocalDefId) -
112112
| sym::likely
113113
| sym::unlikely
114114
| sym::ptr_guaranteed_cmp
115+
| sym::minnumf16
115116
| sym::minnumf32
116117
| sym::minnumf64
118+
| sym::minnumf128
119+
| sym::maxnumf16
117120
| sym::maxnumf32
118-
| sym::rustc_peek
119121
| sym::maxnumf64
122+
| sym::maxnumf128
123+
| sym::rustc_peek
120124
| sym::type_name
121125
| sym::forget
122126
| sym::black_box
@@ -302,50 +306,118 @@ pub fn check_intrinsic_type(
302306
],
303307
Ty::new_unit(tcx),
304308
),
309+
310+
sym::sqrtf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
305311
sym::sqrtf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
306312
sym::sqrtf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
313+
sym::sqrtf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
314+
315+
sym::powif16 => (0, 0, vec![tcx.types.f16, tcx.types.i32], tcx.types.f16),
307316
sym::powif32 => (0, 0, vec![tcx.types.f32, tcx.types.i32], tcx.types.f32),
308317
sym::powif64 => (0, 0, vec![tcx.types.f64, tcx.types.i32], tcx.types.f64),
318+
sym::powif128 => (0, 0, vec![tcx.types.f128, tcx.types.i32], tcx.types.f128),
319+
320+
sym::sinf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
309321
sym::sinf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
310322
sym::sinf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
323+
sym::sinf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
324+
325+
sym::cosf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
311326
sym::cosf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
312327
sym::cosf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
328+
sym::cosf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
329+
330+
sym::powf16 => (0, 0, vec![tcx.types.f16, tcx.types.f16], tcx.types.f16),
313331
sym::powf32 => (0, 0, vec![tcx.types.f32, tcx.types.f32], tcx.types.f32),
314332
sym::powf64 => (0, 0, vec![tcx.types.f64, tcx.types.f64], tcx.types.f64),
333+
sym::powf128 => (0, 0, vec![tcx.types.f128, tcx.types.f128], tcx.types.f128),
334+
335+
sym::expf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
315336
sym::expf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
316337
sym::expf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
338+
sym::expf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
339+
340+
sym::exp2f16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
317341
sym::exp2f32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
318342
sym::exp2f64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
343+
sym::exp2f128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
344+
345+
sym::logf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
319346
sym::logf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
320347
sym::logf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
348+
sym::logf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
349+
350+
sym::log10f16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
321351
sym::log10f32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
322352
sym::log10f64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
353+
sym::log10f128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
354+
355+
sym::log2f16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
323356
sym::log2f32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
324357
sym::log2f64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
358+
sym::log2f128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
359+
360+
sym::fmaf16 => (0, 0, vec![tcx.types.f16, tcx.types.f16, tcx.types.f16], tcx.types.f16),
325361
sym::fmaf32 => (0, 0, vec![tcx.types.f32, tcx.types.f32, tcx.types.f32], tcx.types.f32),
326362
sym::fmaf64 => (0, 0, vec![tcx.types.f64, tcx.types.f64, tcx.types.f64], tcx.types.f64),
363+
sym::fmaf128 => {
364+
(0, 0, vec![tcx.types.f128, tcx.types.f128, tcx.types.f128], tcx.types.f128)
365+
}
366+
367+
sym::fabsf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
327368
sym::fabsf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
328369
sym::fabsf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
370+
sym::fabsf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
371+
372+
sym::minnumf16 => (0, 0, vec![tcx.types.f16, tcx.types.f16], tcx.types.f16),
329373
sym::minnumf32 => (0, 0, vec![tcx.types.f32, tcx.types.f32], tcx.types.f32),
330374
sym::minnumf64 => (0, 0, vec![tcx.types.f64, tcx.types.f64], tcx.types.f64),
375+
sym::minnumf128 => (0, 0, vec![tcx.types.f128, tcx.types.f128], tcx.types.f128),
376+
377+
sym::maxnumf16 => (0, 0, vec![tcx.types.f16, tcx.types.f16], tcx.types.f16),
331378
sym::maxnumf32 => (0, 0, vec![tcx.types.f32, tcx.types.f32], tcx.types.f32),
332379
sym::maxnumf64 => (0, 0, vec![tcx.types.f64, tcx.types.f64], tcx.types.f64),
380+
sym::maxnumf128 => (0, 0, vec![tcx.types.f128, tcx.types.f128], tcx.types.f128),
381+
382+
sym::copysignf16 => (0, 0, vec![tcx.types.f16, tcx.types.f16], tcx.types.f16),
333383
sym::copysignf32 => (0, 0, vec![tcx.types.f32, tcx.types.f32], tcx.types.f32),
334384
sym::copysignf64 => (0, 0, vec![tcx.types.f64, tcx.types.f64], tcx.types.f64),
385+
sym::copysignf128 => (0, 0, vec![tcx.types.f128, tcx.types.f128], tcx.types.f128),
386+
387+
sym::floorf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
335388
sym::floorf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
336389
sym::floorf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
390+
sym::floorf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
391+
392+
sym::ceilf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
337393
sym::ceilf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
338394
sym::ceilf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
395+
sym::ceilf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
396+
397+
sym::truncf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
339398
sym::truncf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
340399
sym::truncf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
400+
sym::truncf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
401+
402+
sym::rintf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
341403
sym::rintf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
342404
sym::rintf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
405+
sym::rintf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
406+
407+
sym::nearbyintf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
343408
sym::nearbyintf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
344409
sym::nearbyintf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
410+
sym::nearbyintf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
411+
412+
sym::roundf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
345413
sym::roundf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
346414
sym::roundf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
415+
sym::roundf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
416+
417+
sym::roundevenf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
347418
sym::roundevenf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
348419
sym::roundevenf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
420+
sym::roundevenf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
349421

350422
sym::volatile_load | sym::unaligned_volatile_load => {
351423
(1, 0, vec![Ty::new_imm_ptr(tcx, param(0))], param(0))

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