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4 files changed

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‎src/test/mir-opt/issue_73223.main.PreCodegen.64bit.diff‎

Lines changed: 17 additions & 90 deletions
Original file line numberDiff line numberDiff line change
@@ -4,112 +4,39 @@
44
fn main() -> () {
55
let mut _0: (); // return place in scope 0 at $DIR/issue-73223.rs:+0:11: +0:11
66
let _1: i32; // in scope 0 at $DIR/issue-73223.rs:+1:9: +1:14
7-
let mut _2: std::option::Option<i32>; // in scope 0 at $DIR/issue-73223.rs:+1:23: +1:30
8-
let _3: i32; // in scope 0 at $DIR/issue-73223.rs:+2:14: +2:15
9-
let mut _5: (&i32, &i32); // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
10-
let mut _6: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
11-
let mut _7: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
12-
let mut _10: bool; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
13-
let mut _11: bool; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
14-
let mut _12: i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
15-
let _14: !; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
16-
let mut _15: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
17-
let _16: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
18-
let mut _17: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
19-
let _18: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
20-
let mut _19: std::option::Option<std::fmt::Arguments>; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
7+
let _2: i32; // in scope 0 at $DIR/issue-73223.rs:+2:14: +2:15
218
scope 1 {
229
debug split => _1; // in scope 1 at $DIR/issue-73223.rs:+1:9: +1:14
23-
let _4: std::option::Option<i32>; // in scope 1 at $DIR/issue-73223.rs:+6:9: +6:14
10+
let _3: std::option::Option<i32>; // in scope 1 at $DIR/issue-73223.rs:+6:9: +6:14
2411
scope 3 {
25-
debug _prev => _4; // in scope 3 at $DIR/issue-73223.rs:+6:9: +6:14
26-
let _8: &i32; // in scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
27-
let _9: &i32; // in scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
28-
let mut _20: &i32; // in scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
12+
debug _prev => _3; // in scope 3 at $DIR/issue-73223.rs:+6:9: +6:14
13+
let _4: &i32; // in scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
14+
let _5: &i32; // in scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
2915
scope 4 {
30-
debug left_val => _8; // in scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
31-
debug right_val => _9; // in scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
32-
let _13: core::panicking::AssertKind; // in scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
16+
debug left_val => _4; // in scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
17+
debug right_val => _5; // in scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
18+
let _6: core::panicking::AssertKind; // in scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3319
scope 5 {
34-
debug kind => _13; // in scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
20+
debug kind => _6; // in scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3521
}
3622
}
3723
}
3824
}
3925
scope 2 {
40-
debug v => _3; // in scope 2 at $DIR/issue-73223.rs:+2:14: +2:15
26+
debug v => _2; // in scope 2 at $DIR/issue-73223.rs:+2:14: +2:15
4127
}
4228

4329
bb0: {
4430
StorageLive(_1); // scope 0 at $DIR/issue-73223.rs:+1:9: +1:14
45-
StorageLive(_2); // scope 0 at $DIR/issue-73223.rs:+1:23: +1:30
46-
Deinit(_2); // scope 0 at $DIR/issue-73223.rs:+1:23: +1:30
47-
((_2 as Some).0: i32) = const 1_i32; // scope 0 at $DIR/issue-73223.rs:+1:23: +1:30
48-
discriminant(_2) = 1; // scope 0 at $DIR/issue-73223.rs:+1:23: +1:30
49-
StorageLive(_3); // scope 0 at $DIR/issue-73223.rs:+2:14: +2:15
50-
_3 = ((_2 as Some).0: i32); // scope 0 at $DIR/issue-73223.rs:+2:14: +2:15
51-
_1 = _3; // scope 2 at $DIR/issue-73223.rs:+2:20: +2:21
52-
StorageDead(_3); // scope 0 at $DIR/issue-73223.rs:+2:20: +2:21
53-
StorageDead(_2); // scope 0 at $DIR/issue-73223.rs:+4:6: +4:7
54-
StorageLive(_4); // scope 1 at $DIR/issue-73223.rs:+6:9: +6:14
31+
StorageLive(_2); // scope 0 at $DIR/issue-73223.rs:+2:14: +2:15
32+
_1 = const 1_i32; // scope 2 at $DIR/issue-73223.rs:+2:20: +2:21
33+
StorageDead(_2); // scope 0 at $DIR/issue-73223.rs:+2:20: +2:21
34+
StorageLive(_3); // scope 1 at $DIR/issue-73223.rs:+6:9: +6:14
35+
StorageLive(_4); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
5536
StorageLive(_5); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
56-
StorageLive(_6); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
57-
_6 = &_1; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
58-
StorageLive(_7); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
59-
_20 = const main::promoted[0]; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
60-
// mir::Constant
61-
// + span: $SRC_DIR/core/src/macros/mod.rs:LL:COL
62-
// + literal: Const { ty: &i32, val: Unevaluated(main, [], Some(promoted[0])) }
63-
_7 = _20; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
64-
Deinit(_5); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
65-
(_5.0: &i32) = move _6; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
66-
(_5.1: &i32) = move _7; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
67-
StorageDead(_7); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
68-
StorageDead(_6); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
69-
StorageLive(_8); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
70-
_8 = (_5.0: &i32); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
71-
StorageLive(_9); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
72-
_9 = (_5.1: &i32); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
73-
StorageLive(_10); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
74-
StorageLive(_11); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
75-
StorageLive(_12); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
76-
_12 = (*_8); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
77-
_11 = Eq(move _12, const 1_i32); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
78-
StorageDead(_12); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
79-
_10 = Not(move _11); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
80-
StorageDead(_11); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
81-
switchInt(move _10) -> [false: bb2, otherwise: bb1]; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
82-
}
83-
84-
bb1: {
85-
StorageLive(_13); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
86-
StorageLive(_14); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
87-
StorageLive(_15); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
88-
StorageLive(_16); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
89-
_16 = _8; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
90-
_15 = _16; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
91-
StorageLive(_17); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
92-
StorageLive(_18); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
93-
_18 = _9; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
94-
_17 = _18; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
95-
StorageLive(_19); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
96-
Deinit(_19); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
97-
discriminant(_19) = 0; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
98-
_14 = core::panicking::assert_failed::<i32, i32>(const core::panicking::AssertKind::Eq, move _15, move _17, move _19); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
99-
// mir::Constant
100-
// + span: $SRC_DIR/core/src/macros/mod.rs:LL:COL
101-
// + literal: Const { ty: for<'r, 's, 't0> fn(core::panicking::AssertKind, &'r i32, &'s i32, Option<Arguments<'t0>>) -> ! {core::panicking::assert_failed::<i32, i32>}, val: Value(<ZST>) }
102-
// mir::Constant
103-
// + span: $SRC_DIR/core/src/macros/mod.rs:LL:COL
104-
// + literal: Const { ty: core::panicking::AssertKind, val: Value(Scalar(0x00)) }
105-
}
106-
107-
bb2: {
108-
StorageDead(_10); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
109-
StorageDead(_9); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
110-
StorageDead(_8); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
11137
StorageDead(_5); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
112-
StorageDead(_4); // scope 1 at $DIR/issue-73223.rs:+8:1: +8:2
38+
StorageDead(_4); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
39+
StorageDead(_3); // scope 1 at $DIR/issue-73223.rs:+8:1: +8:2
11340
StorageDead(_1); // scope 0 at $DIR/issue-73223.rs:+8:1: +8:2
11441
return; // scope 0 at $DIR/issue-73223.rs:+8:2: +8:2
11542
}

‎src/test/mir-opt/issue_73223.main.SimplifyArmIdentity.32bit.diff‎

Lines changed: 24 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
- // MIR for `main` before SimplifyArmIdentity
22
+ // MIR for `main` after SimplifyArmIdentity
3-
3+
44
fn main() -> () {
55
let mut _0: (); // return place in scope 0 at $DIR/issue-73223.rs:+0:11: +0:11
66
let _1: i32; // in scope 0 at $DIR/issue-73223.rs:+1:9: +1:14
@@ -47,7 +47,7 @@
4747
scope 2 {
4848
debug v => _4; // in scope 2 at $DIR/issue-73223.rs:+2:14: +2:15
4949
}
50-
50+
5151
bb0: {
5252
StorageLive(_1); // scope 0 at $DIR/issue-73223.rs:+1:9: +1:14
5353
StorageLive(_2); // scope 0 at $DIR/issue-73223.rs:+1:23: +1:30
@@ -57,29 +57,33 @@
5757
_3 = const 1_isize; // scope 0 at $DIR/issue-73223.rs:+1:23: +1:30
5858
goto -> bb3; // scope 0 at $DIR/issue-73223.rs:+1:17: +1:30
5959
}
60-
60+
6161
bb1: {
6262
nop; // scope 0 at $DIR/issue-73223.rs:+3:17: +3:23
6363
StorageDead(_2); // scope 0 at $DIR/issue-73223.rs:+4:6: +4:7
6464
StorageDead(_1); // scope 0 at $DIR/issue-73223.rs:+8:1: +8:2
6565
return; // scope 0 at $DIR/issue-73223.rs:+8:2: +8:2
6666
}
67-
67+
6868
bb2: {
6969
unreachable; // scope 0 at $DIR/issue-73223.rs:+1:23: +1:30
7070
}
71-
71+
7272
bb3: {
7373
StorageLive(_4); // scope 0 at $DIR/issue-73223.rs:+2:14: +2:15
74-
_4 = ((_2 as Some).0: i32); // scope 0 at $DIR/issue-73223.rs:+2:14: +2:15
75-
_1 = _4; // scope 2 at $DIR/issue-73223.rs:+2:20: +2:21
74+
- _4 = ((_2 as Some).0: i32); // scope 0 at $DIR/issue-73223.rs:+2:14: +2:15
75+
- _1 = _4; // scope 2 at $DIR/issue-73223.rs:+2:20: +2:21
76+
+ _4 = const 1_i32; // scope 0 at $DIR/issue-73223.rs:+2:14: +2:15
77+
+ _1 = const 1_i32; // scope 2 at $DIR/issue-73223.rs:+2:20: +2:21
7678
StorageDead(_4); // scope 0 at $DIR/issue-73223.rs:+2:20: +2:21
7779
StorageDead(_2); // scope 0 at $DIR/issue-73223.rs:+4:6: +4:7
7880
StorageLive(_6); // scope 1 at $DIR/issue-73223.rs:+6:9: +6:14
7981
StorageLive(_7); // scope 1 at $DIR/issue-73223.rs:+6:22: +6:27
80-
_7 = _1; // scope 1 at $DIR/issue-73223.rs:+6:22: +6:27
82+
- _7 = _1; // scope 1 at $DIR/issue-73223.rs:+6:22: +6:27
83+
+ _7 = const 1_i32; // scope 1 at $DIR/issue-73223.rs:+6:22: +6:27
8184
Deinit(_6); // scope 1 at $DIR/issue-73223.rs:+6:17: +6:28
82-
((_6 as Some).0: i32) = move _7; // scope 1 at $DIR/issue-73223.rs:+6:17: +6:28
85+
- ((_6 as Some).0: i32) = move _7; // scope 1 at $DIR/issue-73223.rs:+6:17: +6:28
86+
+ ((_6 as Some).0: i32) = const 1_i32; // scope 1 at $DIR/issue-73223.rs:+6:17: +6:28
8387
discriminant(_6) = 1; // scope 1 at $DIR/issue-73223.rs:+6:17: +6:28
8488
StorageDead(_7); // scope 1 at $DIR/issue-73223.rs:+6:27: +6:28
8589
StorageLive(_8); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
@@ -104,17 +108,21 @@
104108
StorageLive(_15); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
105109
StorageLive(_16); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
106110
StorageLive(_17); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
107-
_17 = (*_13); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
111+
- _17 = (*_13); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
112+
+ _17 = const 1_i32; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
108113
StorageLive(_18); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
109114
_18 = const 1_i32; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
110-
_16 = Eq(move _17, const 1_i32); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
115+
- _16 = Eq(move _17, const 1_i32); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
116+
+ _16 = const true; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
111117
StorageDead(_18); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
112118
StorageDead(_17); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
113-
_15 = Not(move _16); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
119+
- _15 = Not(move _16); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
120+
+ _15 = const false; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
114121
StorageDead(_16); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
115-
switchInt(move _15) -> [false: bb5, otherwise: bb4]; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
122+
- switchInt(move _15) -> [false: bb5, otherwise: bb4]; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
123+
+ goto -> bb5; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
116124
}
117-
125+
118126
bb4: {
119127
StorageLive(_20); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
120128
Deinit(_20); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
@@ -144,7 +152,7 @@
144152
// + span: $SRC_DIR/core/src/macros/mod.rs:LL:COL
145153
// + literal: Const { ty: core::panicking::AssertKind, val: Value(Scalar(0x00)) }
146154
}
147-
155+
148156
bb5: {
149157
nop; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
150158
StorageDead(_15); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
@@ -158,4 +166,4 @@
158166
return; // scope 0 at $DIR/issue-73223.rs:+8:2: +8:2
159167
}
160168
}
161-
169+

‎src/test/mir-opt/issue_73223.main.SimplifyArmIdentity.64bit.diff‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -71,15 +71,15 @@
7171

7272
bb3: {
7373
StorageLive(_4); // scope 0 at $DIR/issue-73223.rs:+2:14: +2:15
74-
_4 = ((_2 as Some).0: i32); // scope 0 at $DIR/issue-73223.rs:+2:14: +2:15
75-
_1 = _4; // scope 2 at $DIR/issue-73223.rs:+2:20: +2:21
74+
_4 = const 1_i32; // scope 0 at $DIR/issue-73223.rs:+2:14: +2:15
75+
_1 = const 1_i32; // scope 2 at $DIR/issue-73223.rs:+2:20: +2:21
7676
StorageDead(_4); // scope 0 at $DIR/issue-73223.rs:+2:20: +2:21
7777
StorageDead(_2); // scope 0 at $DIR/issue-73223.rs:+4:6: +4:7
7878
StorageLive(_6); // scope 1 at $DIR/issue-73223.rs:+6:9: +6:14
7979
StorageLive(_7); // scope 1 at $DIR/issue-73223.rs:+6:22: +6:27
80-
_7 = _1; // scope 1 at $DIR/issue-73223.rs:+6:22: +6:27
80+
_7 = const 1_i32; // scope 1 at $DIR/issue-73223.rs:+6:22: +6:27
8181
Deinit(_6); // scope 1 at $DIR/issue-73223.rs:+6:17: +6:28
82-
((_6 as Some).0: i32) = move _7; // scope 1 at $DIR/issue-73223.rs:+6:17: +6:28
82+
((_6 as Some).0: i32) = const 1_i32; // scope 1 at $DIR/issue-73223.rs:+6:17: +6:28
8383
discriminant(_6) = 1; // scope 1 at $DIR/issue-73223.rs:+6:17: +6:28
8484
StorageDead(_7); // scope 1 at $DIR/issue-73223.rs:+6:27: +6:28
8585
StorageLive(_8); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
@@ -104,15 +104,15 @@
104104
StorageLive(_15); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
105105
StorageLive(_16); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
106106
StorageLive(_17); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
107-
_17 = (*_13); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
107+
_17 = const 1_i32; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
108108
StorageLive(_18); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
109109
_18 = const 1_i32; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
110-
_16 = Eq(move _17, const 1_i32); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
110+
_16 = const true; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
111111
StorageDead(_18); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
112112
StorageDead(_17); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
113-
_15 = Not(move _16); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
113+
_15 = const false; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
114114
StorageDead(_16); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
115-
switchInt(move _15) -> [false: bb5, otherwise: bb4]; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
115+
goto -> bb5; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
116116
}
117117

118118
bb4: {

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