@@ -1825,7 +1825,7 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const {
18251825#else
18261826 uptr err = ucontext->uc_mcontext .gregs [REG_ERR];
18271827#endif // SANITIZER_FREEBSD
1828- return err & PF_WRITE ? WRITE : READ ;
1828+ return err & PF_WRITE ? Write : Read ;
18291829#elif defined(__mips__)
18301830 uint32_t *exception_source;
18311831 uint32_t faulty_instruction;
@@ -1848,7 +1848,7 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const {
18481848 case 0x2a : // swl
18491849 case 0x2e : // swr
18501850#endif
1851- return SignalContext::WRITE ;
1851+ return SignalContext::Write ;
18521852
18531853 case 0x20 : // lb
18541854 case 0x24 : // lbu
@@ -1863,27 +1863,27 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const {
18631863 case 0x22 : // lwl
18641864 case 0x26 : // lwr
18651865#endif
1866- return SignalContext::READ ;
1866+ return SignalContext::Read ;
18671867#if __mips_isa_rev == 6
18681868 case 0x3b : // pcrel
18691869 op_code = (faulty_instruction >> 19 ) & 0x3 ;
18701870 switch (op_code) {
18711871 case 0x1 : // lwpc
18721872 case 0x2 : // lwupc
1873- return SignalContext::READ ;
1873+ return SignalContext::Read ;
18741874 }
18751875#endif
18761876 }
1877- return SignalContext::UNKNOWN ;
1877+ return SignalContext::Unknown ;
18781878#elif defined(__arm__)
18791879 static const uptr FSR_WRITE = 1U << 11 ;
18801880 uptr fsr = ucontext->uc_mcontext .error_code ;
1881- return fsr & FSR_WRITE ? WRITE : READ ;
1881+ return fsr & FSR_WRITE ? Write : Read ;
18821882#elif defined(__aarch64__)
18831883 static const u64 ESR_ELx_WNR = 1U << 6 ;
18841884 u64 esr;
1885- if (!Aarch64GetESR (ucontext, &esr)) return UNKNOWN ;
1886- return esr & ESR_ELx_WNR ? WRITE : READ ;
1885+ if (!Aarch64GetESR (ucontext, &esr)) return Unknown ;
1886+ return esr & ESR_ELx_WNR ? Write : Read ;
18871887#elif defined(__sparc__)
18881888 // Decode the instruction to determine the access type.
18891889 // From OpenSolaris $SRC/uts/sun4/os/trap.c (get_accesstype).
@@ -1899,7 +1899,7 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const {
18991899#endif
19001900#endif
19011901 u32 instr = *(u32 *)pc;
1902- return (instr >> 21 ) & 1 ? WRITE: READ ;
1902+ return (instr >> 21 ) & 1 ? Write: Read ;
19031903#elif defined(__riscv)
19041904#if SANITIZER_FREEBSD
19051905 unsigned long pc = ucontext->uc_mcontext .mc_gpregs .gp_sepc ;
@@ -1919,7 +1919,7 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const {
19191919#if __riscv_xlen == 64
19201920 case 0b10'011 : // c.ldsp (rd != x0)
19211921#endif
1922- return rd ? SignalContext::READ : SignalContext::UNKNOWN ;
1922+ return rd ? SignalContext::Read : SignalContext::Unknown ;
19231923 case 0b00'010 : // c.lw
19241924#if __riscv_flen >= 32 && __riscv_xlen == 32
19251925 case 0b10'011 : // c.flwsp
@@ -1931,7 +1931,7 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const {
19311931 case 0b00'001 : // c.fld
19321932 case 0b10'001 : // c.fldsp
19331933#endif
1934- return SignalContext::READ ;
1934+ return SignalContext::Read ;
19351935 case 0b00'110 : // c.sw
19361936 case 0b10'110 : // c.swsp
19371937#if __riscv_flen >= 32 || __riscv_xlen == 64
@@ -1942,9 +1942,9 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const {
19421942 case 0b00'101 : // c.fsd
19431943 case 0b10'101 : // c.fsdsp
19441944#endif
1945- return SignalContext::WRITE ;
1945+ return SignalContext::Write ;
19461946 default :
1947- return SignalContext::UNKNOWN ;
1947+ return SignalContext::Unknown ;
19481948 }
19491949 }
19501950#endif
@@ -1962,9 +1962,9 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const {
19621962#endif
19631963 case 0b100 : // lbu
19641964 case 0b101 : // lhu
1965- return SignalContext::READ ;
1965+ return SignalContext::Read ;
19661966 default :
1967- return SignalContext::UNKNOWN ;
1967+ return SignalContext::Unknown ;
19681968 }
19691969 case 0b0100011 : // stores
19701970 switch (funct3) {
@@ -1974,9 +1974,9 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const {
19741974#if __riscv_xlen == 64
19751975 case 0b011 : // sd
19761976#endif
1977- return SignalContext::WRITE ;
1977+ return SignalContext::Write ;
19781978 default :
1979- return SignalContext::UNKNOWN ;
1979+ return SignalContext::Unknown ;
19801980 }
19811981#if __riscv_flen >= 32
19821982 case 0b0000111 : // floating-point loads
@@ -1985,27 +1985,27 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const {
19851985#if __riscv_flen == 64
19861986 case 0b011 : // fld
19871987#endif
1988- return SignalContext::READ ;
1988+ return SignalContext::Read ;
19891989 default :
1990- return SignalContext::UNKNOWN ;
1990+ return SignalContext::Unknown ;
19911991 }
19921992 case 0b0100111 : // floating-point stores
19931993 switch (funct3) {
19941994 case 0b010 : // fsw
19951995#if __riscv_flen == 64
19961996 case 0b011 : // fsd
19971997#endif
1998- return SignalContext::WRITE ;
1998+ return SignalContext::Write ;
19991999 default :
2000- return SignalContext::UNKNOWN ;
2000+ return SignalContext::Unknown ;
20012001 }
20022002#endif
20032003 default :
2004- return SignalContext::UNKNOWN ;
2004+ return SignalContext::Unknown ;
20052005 }
20062006#else
20072007 (void )ucontext;
2008- return UNKNOWN ; // FIXME: Implement.
2008+ return Unknown ; // FIXME: Implement.
20092009#endif
20102010}
20112011
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