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[WebAssembly] Codegen for i64x2.extend_{low,high}_i32x4_{s,u}
Removes the builtins and intrinsics used to opt in to using these instructions and replaces them with normal ISel patterns now that they are no longer prototypes. Differential Revision: https://reviews.llvm.org/D100402
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+61
-116
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8 files changed

+61
-116
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‎clang/include/clang/Basic/BuiltinsWebAssembly.def‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -191,11 +191,6 @@ TARGET_BUILTIN(__builtin_wasm_narrow_u_i8x16_i16x8, "V16UcV8UsV8Us", "nc", "simd
191191
TARGET_BUILTIN(__builtin_wasm_narrow_s_i16x8_i32x4, "V8sV4iV4i", "nc", "simd128")
192192
TARGET_BUILTIN(__builtin_wasm_narrow_u_i16x8_i32x4, "V8UsV4UiV4Ui", "nc", "simd128")
193193

194-
TARGET_BUILTIN(__builtin_wasm_extend_low_s_i32x4_i64x2, "V2LLiV4i", "nc", "simd128")
195-
TARGET_BUILTIN(__builtin_wasm_extend_high_s_i32x4_i64x2, "V2LLiV4i", "nc", "simd128")
196-
TARGET_BUILTIN(__builtin_wasm_extend_low_u_i32x4_i64x2, "V2LLUiV4Ui", "nc", "simd128")
197-
TARGET_BUILTIN(__builtin_wasm_extend_high_u_i32x4_i64x2, "V2LLUiV4Ui", "nc", "simd128")
198-
199194
TARGET_BUILTIN(__builtin_wasm_trunc_sat_zero_s_f64x2_i32x4, "V4iV2d", "nc", "simd128")
200195
TARGET_BUILTIN(__builtin_wasm_trunc_sat_zero_u_f64x2_i32x4, "V4UiV2d", "nc", "simd128")
201196
TARGET_BUILTIN(__builtin_wasm_demote_zero_f64x2_f32x4, "V4fV2d", "nc", "simd128")

‎clang/lib/CodeGen/CGBuiltin.cpp‎

Lines changed: 0 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -17158,29 +17158,6 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
1715817158
CGM.getIntrinsic(IntNo, {ConvertType(E->getType()), Low->getType()});
1715917159
return Builder.CreateCall(Callee, {Low, High});
1716017160
}
17161-
case WebAssembly::BI__builtin_wasm_extend_low_s_i32x4_i64x2:
17162-
case WebAssembly::BI__builtin_wasm_extend_high_s_i32x4_i64x2:
17163-
case WebAssembly::BI__builtin_wasm_extend_low_u_i32x4_i64x2:
17164-
case WebAssembly::BI__builtin_wasm_extend_high_u_i32x4_i64x2: {
17165-
Value *Vec = EmitScalarExpr(E->getArg(0));
17166-
unsigned IntNo;
17167-
switch (BuiltinID) {
17168-
case WebAssembly::BI__builtin_wasm_extend_low_s_i32x4_i64x2:
17169-
IntNo = Intrinsic::wasm_extend_low_signed;
17170-
break;
17171-
case WebAssembly::BI__builtin_wasm_extend_high_s_i32x4_i64x2:
17172-
IntNo = Intrinsic::wasm_extend_high_signed;
17173-
break;
17174-
case WebAssembly::BI__builtin_wasm_extend_low_u_i32x4_i64x2:
17175-
IntNo = Intrinsic::wasm_extend_low_unsigned;
17176-
break;
17177-
case WebAssembly::BI__builtin_wasm_extend_high_u_i32x4_i64x2:
17178-
IntNo = Intrinsic::wasm_extend_high_unsigned;
17179-
break;
17180-
}
17181-
Function *Callee = CGM.getIntrinsic(IntNo);
17182-
return Builder.CreateCall(Callee, Vec);
17183-
}
1718417161
case WebAssembly::BI__builtin_wasm_trunc_sat_zero_s_f64x2_i32x4:
1718517162
case WebAssembly::BI__builtin_wasm_trunc_sat_zero_u_f64x2_i32x4: {
1718617163
Value *Vec = EmitScalarExpr(E->getArg(0));

‎clang/test/CodeGen/builtins-wasm.c‎

Lines changed: 0 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -890,30 +890,6 @@ u16x8 narrow_u_i16x8_i32x4(u32x4 low, u32x4 high) {
890890
// WEBASSEMBLY: ret
891891
}
892892

893-
i64x2 extend_low_s_i32x4_i64x2(i32x4 x) {
894-
return __builtin_wasm_extend_low_s_i32x4_i64x2(x);
895-
// WEBASSEMBLY: call <2 x i64> @llvm.wasm.extend.low.signed(<4 x i32> %x)
896-
// WEBASSEMBLY: ret
897-
}
898-
899-
i64x2 extend_high_s_i32x4_i64x2(i32x4 x) {
900-
return __builtin_wasm_extend_high_s_i32x4_i64x2(x);
901-
// WEBASSEMBLY: call <2 x i64> @llvm.wasm.extend.high.signed(<4 x i32> %x)
902-
// WEBASSEMBLY: ret
903-
}
904-
905-
u64x2 extend_low_u_i32x4_i64x2(u32x4 x) {
906-
return __builtin_wasm_extend_low_u_i32x4_i64x2(x);
907-
// WEBASSEMBLY: call <2 x i64> @llvm.wasm.extend.low.unsigned(<4 x i32> %x)
908-
// WEBASSEMBLY: ret
909-
}
910-
911-
u64x2 extend_high_u_i32x4_i64x2(u32x4 x) {
912-
return __builtin_wasm_extend_high_u_i32x4_i64x2(x);
913-
// WEBASSEMBLY: call <2 x i64> @llvm.wasm.extend.high.unsigned(<4 x i32> %x)
914-
// WEBASSEMBLY: ret
915-
}
916-
917893
i32x4 trunc_sat_zero_s_f64x2_i32x4(f64x2 x) {
918894
return __builtin_wasm_trunc_sat_zero_s_f64x2_i32x4(x);
919895
// WEBASSEMBLY: call <4 x i32> @llvm.wasm.trunc.sat.zero.signed(<2 x double> %x)

‎llvm/include/llvm/IR/IntrinsicsWebAssembly.td‎

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -157,17 +157,6 @@ def int_wasm_narrow_unsigned :
157157
[llvm_anyvector_ty, LLVMMatchType<1>],
158158
[IntrNoMem, IntrSpeculatable]>;
159159

160-
// TODO: Replace these intrinsics with normal ISel patterns once i32x4 to i64x2
161-
// extending is merged to the proposal.
162-
def int_wasm_extend_low_signed :
163-
Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem, IntrSpeculatable]>;
164-
def int_wasm_extend_high_signed :
165-
Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem, IntrSpeculatable]>;
166-
def int_wasm_extend_low_unsigned :
167-
Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem, IntrSpeculatable]>;
168-
def int_wasm_extend_high_unsigned :
169-
Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem, IntrSpeculatable]>;
170-
171160
def int_wasm_q15mulr_sat_signed :
172161
Intrinsic<[llvm_v8i16_ty],
173162
[llvm_v8i16_ty, llvm_v8i16_ty],

‎llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1994,8 +1994,8 @@ performVectorExtendCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
19941994
return SDValue();
19951995
auto Index = IndexNode->getZExtValue();
19961996

1997-
// Only v8i8 and v4i16 extracts can be widened, and only if the extracted
1998-
// subvector is the low or high half of its source.
1997+
// Only v8i8, v4i16, and v2i32 extracts can be widened, and only if the
1998+
// extracted subvector is the low or high half of its source.
19991999
EVT ResVT = N->getValueType(0);
20002000
if (ResVT == MVT::v8i16) {
20012001
if (Extract.getValueType() != MVT::v8i8 ||
@@ -2005,6 +2005,10 @@ performVectorExtendCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
20052005
if (Extract.getValueType() != MVT::v4i16 ||
20062006
Source.getValueType() != MVT::v8i16 || (Index != 0 && Index != 4))
20072007
return SDValue();
2008+
} else if (ResVT == MVT::v2i64) {
2009+
if (Extract.getValueType() != MVT::v2i32 ||
2010+
Source.getValueType() != MVT::v4i32 || (Index != 0 && Index != 2))
2011+
return SDValue();
20082012
} else {
20092013
return SDValue();
20102014
}

‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td‎

Lines changed: 3 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1138,17 +1138,9 @@ multiclass SIMDExtend<Vec vec, bits<32> baseInst> {
11381138
"extend_high_"#vec.split.prefix#"_u", !add(baseInst, 3)>;
11391139
}
11401140

1141-
defm "" : SIMDExtend<I16x8, 135>;
1142-
defm "" : SIMDExtend<I32x4, 167>;
1143-
1144-
defm "" : SIMDConvert<I64x2, I32x4, int_wasm_extend_low_signed,
1145-
"extend_low_i32x4_s", 199>;
1146-
defm "" : SIMDConvert<I64x2, I32x4, int_wasm_extend_high_signed,
1147-
"extend_high_i32x4_s", 200>;
1148-
defm "" : SIMDConvert<I64x2, I32x4, int_wasm_extend_low_unsigned,
1149-
"extend_low_i32x4_u", 201>;
1150-
defm "" : SIMDConvert<I64x2, I32x4, int_wasm_extend_high_unsigned,
1151-
"extend_high_i32x4_u", 202>;
1141+
defm "" : SIMDExtend<I16x8, 0x87>;
1142+
defm "" : SIMDExtend<I32x4, 0xa7>;
1143+
defm "" : SIMDExtend<I64x2, 0xc7>;
11521144

11531145
// Narrowing operations
11541146
multiclass SIMDNarrow<Vec vec, bits<32> baseInst> {

‎llvm/test/CodeGen/WebAssembly/simd-extending.ll‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,58 @@ define <4 x i32> @extend_high_i16x8_u(<8 x i16> %v) {
110110
ret <4 x i32> %extended
111111
}
112112

113+
define <2 x i64> @extend_low_i32x4_s(<4 x i32> %v) {
114+
; CHECK-LABEL: extend_low_i32x4_s:
115+
; CHECK: .functype extend_low_i32x4_s (v128) -> (v128)
116+
; CHECK-NEXT: # %bb.0:
117+
; CHECK-NEXT: local.get 0
118+
; CHECK-NEXT: i64x2.extend_low_i32x4_s
119+
; CHECK-NEXT: # fallthrough-return
120+
%low = shufflevector <4 x i32> %v, <4 x i32> undef,
121+
<2 x i32> <i32 0, i32 1>
122+
%extended = sext <2 x i32> %low to <2 x i64>
123+
ret <2 x i64> %extended
124+
}
125+
126+
define <2 x i64> @extend_low_i32x4_u(<4 x i32> %v) {
127+
; CHECK-LABEL: extend_low_i32x4_u:
128+
; CHECK: .functype extend_low_i32x4_u (v128) -> (v128)
129+
; CHECK-NEXT: # %bb.0:
130+
; CHECK-NEXT: local.get 0
131+
; CHECK-NEXT: i64x2.extend_low_i32x4_u
132+
; CHECK-NEXT: # fallthrough-return
133+
%low = shufflevector <4 x i32> %v, <4 x i32> undef,
134+
<2 x i32> <i32 0, i32 1>
135+
%extended = zext <2 x i32> %low to <2 x i64>
136+
ret <2 x i64> %extended
137+
}
138+
139+
define <2 x i64> @extend_high_i32x4_s(<4 x i32> %v) {
140+
; CHECK-LABEL: extend_high_i32x4_s:
141+
; CHECK: .functype extend_high_i32x4_s (v128) -> (v128)
142+
; CHECK-NEXT: # %bb.0:
143+
; CHECK-NEXT: local.get 0
144+
; CHECK-NEXT: i64x2.extend_high_i32x4_s
145+
; CHECK-NEXT: # fallthrough-return
146+
%low = shufflevector <4 x i32> %v, <4 x i32> undef,
147+
<2 x i32> <i32 2, i32 3>
148+
%extended = sext <2 x i32> %low to <2 x i64>
149+
ret <2 x i64> %extended
150+
}
151+
152+
define <2 x i64> @extend_high_i32x4_u(<4 x i32> %v) {
153+
; CHECK-LABEL: extend_high_i32x4_u:
154+
; CHECK: .functype extend_high_i32x4_u (v128) -> (v128)
155+
; CHECK-NEXT: # %bb.0:
156+
; CHECK-NEXT: local.get 0
157+
; CHECK-NEXT: i64x2.extend_high_i32x4_u
158+
; CHECK-NEXT: # fallthrough-return
159+
%low = shufflevector <4 x i32> %v, <4 x i32> undef,
160+
<2 x i32> <i32 2, i32 3>
161+
%extended = zext <2 x i32> %low to <2 x i64>
162+
ret <2 x i64> %extended
163+
}
164+
113165
;; Also test that similar patterns with offsets not corresponding to
114166
;; the low or high half are correctly expanded.
115167

‎llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll‎

Lines changed: 0 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -553,46 +553,6 @@ define <4 x i32> @trunc_sat_zero_unsigned_v4i32(<2 x double> %a) {
553553
; ==============================================================================
554554
; 2 x i64
555555
; ==============================================================================
556-
; CHECK-LABEL: extend_low_s_v2i64:
557-
; CHECK-NEXT: .functype extend_low_s_v2i64 (v128) -> (v128){{$}}
558-
; CHECK-NEXT: i64x2.extend_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
559-
; CHECK-NEXT: return $pop[[R]]{{$}}
560-
declare <2 x i64> @llvm.wasm.extend.low.signed(<4 x i32>)
561-
define <2 x i64> @extend_low_s_v2i64(<4 x i32> %x) {
562-
%a = call <2 x i64> @llvm.wasm.extend.low.signed(<4 x i32> %x)
563-
ret <2 x i64> %a
564-
}
565-
566-
; CHECK-LABEL: extend_high_s_v2i64:
567-
; CHECK-NEXT: .functype extend_high_s_v2i64 (v128) -> (v128){{$}}
568-
; CHECK-NEXT: i64x2.extend_high_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
569-
; CHECK-NEXT: return $pop[[R]]{{$}}
570-
declare <2 x i64> @llvm.wasm.extend.high.signed(<4 x i32>)
571-
define <2 x i64> @extend_high_s_v2i64(<4 x i32> %x) {
572-
%a = call <2 x i64> @llvm.wasm.extend.high.signed(<4 x i32> %x)
573-
ret <2 x i64> %a
574-
}
575-
576-
; CHECK-LABEL: extend_low_u_v2i64:
577-
; CHECK-NEXT: .functype extend_low_u_v2i64 (v128) -> (v128){{$}}
578-
; CHECK-NEXT: i64x2.extend_low_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
579-
; CHECK-NEXT: return $pop[[R]]{{$}}
580-
declare <2 x i64> @llvm.wasm.extend.low.unsigned(<4 x i32>)
581-
define <2 x i64> @extend_low_u_v2i64(<4 x i32> %x) {
582-
%a = call <2 x i64> @llvm.wasm.extend.low.unsigned(<4 x i32> %x)
583-
ret <2 x i64> %a
584-
}
585-
586-
; CHECK-LABEL: extend_high_u_v2i64:
587-
; CHECK-NEXT: .functype extend_high_u_v2i64 (v128) -> (v128){{$}}
588-
; CHECK-NEXT: i64x2.extend_high_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
589-
; CHECK-NEXT: return $pop[[R]]{{$}}
590-
declare <2 x i64> @llvm.wasm.extend.high.unsigned(<4 x i32>)
591-
define <2 x i64> @extend_high_u_v2i64(<4 x i32> %x) {
592-
%a = call <2 x i64> @llvm.wasm.extend.high.unsigned(<4 x i32> %x)
593-
ret <2 x i64> %a
594-
}
595-
596556
; CHECK-LABEL: extmul_low_s_v2i64:
597557
; CHECK-NEXT: .functype extmul_low_s_v2i64 (v128, v128) -> (v128){{$}}
598558
; CHECK-NEXT: i64x2.extmul_low_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}

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