Rename cirq_ft.Registers to cirq_ft.Signature to match data types in Qualtran (#6300)

* Rename cirq_ft.Registers to cirq_ft.Signature to match data types in Qualtran

* Fix coverage tests

---------

Co-authored-by: Fionn Malone <[email protected]>

Author: tanujkhattar

cirq-ft/cirq_ft/__init__.py

@@ -47,7 +47,7 @@
     GateWithRegisters,
     GreedyQubitManager,
     Register,
-    Registers,
+    Signature,
     SelectionRegister,
     TComplexity,
     map_clean_and_borrowable_qubits,

cirq-ft/cirq_ft/algos/and_gate.ipynb

@@ -66,7 +66,7 @@
     "from cirq_ft import And, infra\n",
     "\n",
     "gate = And()\n",
-    "r = gate.registers\n",
+    "r = gate.signature\n",
     "quregs = infra.get_named_qubits(r)\n",
     "operation = gate.on_registers(**quregs)\n",
     "circuit = cirq.Circuit(operation)\n",

cirq-ft/cirq_ft/algos/and_gate.py

@@ -60,8 +60,8 @@ def _validate_cv(self, attribute, value):
             raise ValueError(f"And gate needs at-least 2 control values, supplied {value} instead.")
 
     @cached_property
-    def registers(self) -> infra.Registers:
-        return infra.Registers.build(control=len(self.cv), ancilla=len(self.cv) - 2, target=1)
+    def signature(self) -> infra.Signature:
+        return infra.Signature.build(control=len(self.cv), ancilla=len(self.cv) - 2, target=1)
 
     def __pow__(self, power: int) -> "And":
         if power == 1:

cirq-ft/cirq_ft/algos/and_gate_test.py

@@ -45,17 +45,17 @@ def random_cv(n: int) -> List[int]:
 @pytest.mark.parametrize("cv", [[1] * 3, random_cv(5), random_cv(6), random_cv(7)])
 def test_multi_controlled_and_gate(cv: List[int]):
     gate = cirq_ft.And(cv)
-    r = gate.registers
-    assert r['ancilla'].total_bits() == r['control'].total_bits() - 2
+    r = gate.signature
+    assert r.get_left('ancilla').total_bits() == r.get_left('control').total_bits() - 2
     quregs = infra.get_named_qubits(r)
     and_op = gate.on_registers(**quregs)
     circuit = cirq.Circuit(and_op)
 
     input_controls = [cv] + [random_cv(len(cv)) for _ in range(10)]
-    qubit_order = infra.merge_qubits(gate.registers, **quregs)
+    qubit_order = infra.merge_qubits(gate.signature, **quregs)
 
     for input_control in input_controls:
-        initial_state = input_control + [0] * (r['ancilla'].total_bits() + 1)
+        initial_state = input_control + [0] * (r.get_left('ancilla').total_bits() + 1)
         result = cirq.Simulator(dtype=np.complex128).simulate(
             circuit, initial_state=initial_state, qubit_order=qubit_order
         )
@@ -78,7 +78,7 @@ def test_multi_controlled_and_gate(cv: List[int]):
 
 def test_and_gate_diagram():
     gate = cirq_ft.And((1, 0, 1, 0, 1, 0))
-    qubit_regs = infra.get_named_qubits(gate.registers)
+    qubit_regs = infra.get_named_qubits(gate.signature)
     op = gate.on_registers(**qubit_regs)
     # Qubit order should be alternating (control, ancilla) pairs.
     c_and_a = sum(zip(qubit_regs["control"][1:], qubit_regs["ancilla"]), ()) + (

cirq-ft/cirq_ft/algos/apply_gate_to_lth_target.ipynb

@@ -69,9 +69,9 @@
     "`selection`-th qubit of `target` all controlled by the `control` register.\n",
     "\n",
     "#### Parameters\n",
-    " - `selection_regs`: Indexing `select` registers of type Tuple[`SelectionRegister`, ...]. It also contains information about the iteration length of each selection register.\n",
+    " - `selection_regs`: Indexing `select` signature of type Tuple[`SelectionRegister`, ...]. It also contains information about the iteration length of each selection register.\n",
     " - `nth_gate`: A function mapping the composite selection index to a single-qubit gate.\n",
-    " - `control_regs`: Control registers for constructing a controlled version of the gate.\n"
+    " - `control_regs`: Control signature for constructing a controlled version of the gate.\n"
    ]
   },
   {
@@ -91,7 +91,7 @@
     "apply_z_to_odd = cirq_ft.ApplyGateToLthQubit(\n",
     "    cirq_ft.SelectionRegister('selection', 3, 4),\n",
     "    nth_gate=_z_to_odd,\n",
-    "    control_regs=cirq_ft.Registers.build(control=2),\n",
+    "    control_regs=cirq_ft.Signature.build(control=2),\n",
     ")\n",
     "\n",
     "g = cq_testing.GateHelper(\n",

cirq-ft/cirq_ft/algos/apply_gate_to_lth_target.py

@@ -37,10 +37,10 @@ class ApplyGateToLthQubit(unary_iteration_gate.UnaryIterationGate):
     `selection`-th qubit of `target` all controlled by the `control` register.
 
     Args:
-        selection_regs: Indexing `select` registers of type Tuple[`SelectionRegisters`, ...].
+        selection_regs: Indexing `select` signature of type Tuple[`SelectionRegisters`, ...].
             It also contains information about the iteration length of each selection register.
         nth_gate: A function mapping the composite selection index to a single-qubit gate.
-        control_regs: Control registers for constructing a controlled version of the gate.
+        control_regs: Control signature for constructing a controlled version of the gate.
 
     References:
             [Encoding Electronic Spectra in Quantum Circuits with Linear T Complexity]

cirq-ft/cirq_ft/algos/apply_gate_to_lth_target_test.py

@@ -54,10 +54,10 @@ def test_apply_gate_to_lth_qubit_diagram():
     gate = cirq_ft.ApplyGateToLthQubit(
         cirq_ft.SelectionRegister('selection', 3, 5),
         lambda n: cirq.Z if n & 1 else cirq.I,
-        control_regs=cirq_ft.Registers.build(control=2),
+        control_regs=cirq_ft.Signature.build(control=2),
     )
-    circuit = cirq.Circuit(gate.on_registers(**infra.get_named_qubits(gate.registers)))
-    qubits = list(q for v in infra.get_named_qubits(gate.registers).values() for q in v)
+    circuit = cirq.Circuit(gate.on_registers(**infra.get_named_qubits(gate.signature)))
+    qubits = list(q for v in infra.get_named_qubits(gate.signature).values() for q in v)
     cirq.testing.assert_has_diagram(
         circuit,
         """
@@ -89,11 +89,11 @@ def test_apply_gate_to_lth_qubit_make_on():
     gate = cirq_ft.ApplyGateToLthQubit(
         cirq_ft.SelectionRegister('selection', 3, 5),
         lambda n: cirq.Z if n & 1 else cirq.I,
-        control_regs=cirq_ft.Registers.build(control=2),
+        control_regs=cirq_ft.Signature.build(control=2),
     )
-    op = gate.on_registers(**infra.get_named_qubits(gate.registers))
+    op = gate.on_registers(**infra.get_named_qubits(gate.signature))
     op2 = cirq_ft.ApplyGateToLthQubit.make_on(
-        nth_gate=lambda n: cirq.Z if n & 1 else cirq.I, **infra.get_named_qubits(gate.registers)
+        nth_gate=lambda n: cirq.Z if n & 1 else cirq.I, **infra.get_named_qubits(gate.signature)
     )
     # Note: ApplyGateToLthQubit doesn't support value equality.
     assert op.qubits == op2.qubits

cirq-ft/cirq_ft/algos/arithmetic_gates.py

@@ -137,7 +137,7 @@ class BiQubitsMixer(infra.GateWithRegisters):
     """Implements the COMPARE2 (Fig. 1) https://static-content.springer.com/esm/art%3A10.1038%2Fs41534-018-0071-5/MediaObjects/41534_2018_71_MOESM1_ESM.pdf
 
     This gates mixes the values in a way that preserves the result of comparison.
-    The registers being compared are 2-qubit registers where
+    The signature being compared are 2-qubit signature where
         x = 2*x_msb + x_lsb
         y = 2*y_msb + y_lsb
     The Gate mixes the 4 qubits so that sign(x - y) = sign(x_lsb' - y_lsb') where x_lsb' and y_lsb'
@@ -147,8 +147,8 @@ class BiQubitsMixer(infra.GateWithRegisters):
     adjoint: bool = False
 
     @cached_property
-    def registers(self) -> infra.Registers:
-        return infra.Registers.build(x=2, y=2, ancilla=3)
+    def signature(self) -> infra.Signature:
+        return infra.Signature.build(x=2, y=2, ancilla=3)
 
     def __repr__(self) -> str:
         return f'cirq_ft.algos.BiQubitsMixer({self.adjoint})'
@@ -221,8 +221,8 @@ class SingleQubitCompare(infra.GateWithRegisters):
     adjoint: bool = False
 
     @cached_property
-    def registers(self) -> infra.Registers:
-        return infra.Registers.build(a=1, b=1, less_than=1, greater_than=1)
+    def signature(self) -> infra.Signature:
+        return infra.Signature.build(a=1, b=1, less_than=1, greater_than=1)
 
     def __repr__(self) -> str:
         return f'cirq_ft.algos.SingleQubitCompare({self.adjoint})'
@@ -437,7 +437,7 @@ def _has_unitary_(self):
 class ContiguousRegisterGate(cirq.ArithmeticGate):
     """Applies U|x>|y>|0> -> |x>|y>|x(x-1)/2 + y>
 
-    This is useful in the case when $|x>$ and $|y>$ represent two selection registers such that
+    This is useful in the case when $|x>$ and $|y>$ represent two selection signature such that
      $y < x$. For example, imagine a classical for-loop over two variables $x$ and $y$:
 
     >>> N = 10
@@ -460,8 +460,8 @@ class ContiguousRegisterGate(cirq.ArithmeticGate):
      Note that both the for-loops iterate over the same ranges and in the same order. The only
      difference is that the second loop is a "flattened" version of the first one.
 
-     Such a flattening of selection registers is useful when we want to load multi dimensional
-     data to a target register which is indexed on selection registers $x$ and $y$ such that
+     Such a flattening of selection signature is useful when we want to load multi dimensional
+     data to a target register which is indexed on selection signature $x$ and $y$ such that
      $0<= y <= x < N$ and we want to use a `SelectSwapQROM` to laod this data; which gives a
      sqrt-speedup over a traditional QROM at the cost of using more memory and loading chunks
      of size `sqrt(N)` in a single iteration. See the reference for more details.

cirq-ft/cirq_ft/algos/generic_select_test.py

@@ -256,7 +256,7 @@ def test_generic_select_consistent_protocols_and_controlled():
 
     # Build GenericSelect gate.
     gate = cirq_ft.GenericSelect(select_bitsize, num_sites, dps_hamiltonian)
-    op = gate.on_registers(**infra.get_named_qubits(gate.registers))
+    op = gate.on_registers(**infra.get_named_qubits(gate.signature))
     cirq.testing.assert_equivalent_repr(gate, setup_code='import cirq\nimport cirq_ft')
 
     # Build controlled gate

cirq-ft/cirq_ft/algos/hubbard_model.ipynb

@@ -171,7 +171,7 @@
     "    logN = (2 * (dim - 1).bit_length() + 1)\n",
     "    # 2 * (4 * (N - 1)) : From 2 SelectMajoranaFermion gates.\n",
     "    # 4 * (N/2) : From 1 mulit-controlled ApplyToLthQubit gate on N / 2 targets.\n",
-    "    # 2 * 7 * logN : From 2 CSWAPS on logN qubits corresponding to (p, q) select registers.\n",
+    "    # 2 * 7 * logN : From 2 CSWAPS on logN qubits corresponding to (p, q) select signature.\n",
     "    assert cost.t == 10 * N + 14 * logN - 8\n",
     "    assert cost.rotations == 0\n",
     "    x.append(N)\n",