2121
2222#define HW_ATL_UCP_0X370_REG 0x0370U
2323
24+ #define HW_ATL_MIF_CMD 0x0200U
25+ #define HW_ATL_MIF_ADDR 0x0208U
26+ #define HW_ATL_MIF_VAL 0x020CU
27+
2428#define HW_ATL_FW_SM_RAM 0x2U
2529#define HW_ATL_MPI_FW_VERSION 0x18
2630#define HW_ATL_MPI_CONTROL_ADR 0x0368U
@@ -79,16 +83,15 @@ int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops)
7983
8084static int hw_atl_utils_soft_reset_flb (struct aq_hw_s * self )
8185{
86+ u32 gsr , val ;
8287 int k = 0 ;
83- u32 gsr ;
8488
8589 aq_hw_write_reg (self , 0x404 , 0x40e1 );
8690 AQ_HW_SLEEP (50 );
8791
8892 /* Cleanup SPI */
89- aq_hw_write_reg (self , 0x534 , 0xA0 );
90- aq_hw_write_reg (self , 0x100 , 0x9F );
91- aq_hw_write_reg (self , 0x100 , 0x809F );
93+ val = aq_hw_read_reg (self , 0x53C );
94+ aq_hw_write_reg (self , 0x53C , val | 0x10 );
9295
9396 gsr = aq_hw_read_reg (self , HW_ATL_GLB_SOFT_RES_ADR );
9497 aq_hw_write_reg (self , HW_ATL_GLB_SOFT_RES_ADR , (gsr & 0xBFFF ) | 0x8000 );
@@ -97,7 +100,14 @@ static int hw_atl_utils_soft_reset_flb(struct aq_hw_s *self)
97100 aq_hw_write_reg (self , 0x404 , 0x80e0 );
98101 aq_hw_write_reg (self , 0x32a8 , 0x0 );
99102 aq_hw_write_reg (self , 0x520 , 0x1 );
103+
104+ /* Reset SPI again because of possible interrupted SPI burst */
105+ val = aq_hw_read_reg (self , 0x53C );
106+ aq_hw_write_reg (self , 0x53C , val | 0x10 );
100107 AQ_HW_SLEEP (10 );
108+ /* Clear SPI reset state */
109+ aq_hw_write_reg (self , 0x53C , val & ~0x10 );
110+
101111 aq_hw_write_reg (self , 0x404 , 0x180e0 );
102112
103113 for (k = 0 ; k < 1000 ; k ++ ) {
@@ -141,13 +151,15 @@ static int hw_atl_utils_soft_reset_flb(struct aq_hw_s *self)
141151 aq_pr_err ("FW kickstart failed\n" );
142152 return - EIO ;
143153 }
154+ /* Old FW requires fixed delay after init */
155+ AQ_HW_SLEEP (15 );
144156
145157 return 0 ;
146158}
147159
148160static int hw_atl_utils_soft_reset_rbl (struct aq_hw_s * self )
149161{
150- u32 gsr , rbl_status ;
162+ u32 gsr , val , rbl_status ;
151163 int k ;
152164
153165 aq_hw_write_reg (self , 0x404 , 0x40e1 );
@@ -157,6 +169,10 @@ static int hw_atl_utils_soft_reset_rbl(struct aq_hw_s *self)
157169 /* Alter RBL status */
158170 aq_hw_write_reg (self , 0x388 , 0xDEAD );
159171
172+ /* Cleanup SPI */
173+ val = aq_hw_read_reg (self , 0x53C );
174+ aq_hw_write_reg (self , 0x53C , val | 0x10 );
175+
160176 /* Global software reset*/
161177 hw_atl_rx_rx_reg_res_dis_set (self , 0U );
162178 hw_atl_tx_tx_reg_res_dis_set (self , 0U );
@@ -204,6 +220,8 @@ static int hw_atl_utils_soft_reset_rbl(struct aq_hw_s *self)
204220 aq_pr_err ("FW kickstart failed\n" );
205221 return - EIO ;
206222 }
223+ /* Old FW requires fixed delay after init */
224+ AQ_HW_SLEEP (15 );
207225
208226 return 0 ;
209227}
@@ -255,18 +273,22 @@ int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
255273 }
256274 }
257275
258- aq_hw_write_reg (self , 0x00000208U , a );
259-
260- for (++ cnt ; -- cnt ;) {
261- u32 i = 0U ;
276+ aq_hw_write_reg (self , HW_ATL_MIF_ADDR , a );
262277
263- aq_hw_write_reg (self , 0x00000200U , 0x00008000U );
278+ for (++ cnt ; -- cnt && !err ;) {
279+ aq_hw_write_reg (self , HW_ATL_MIF_CMD , 0x00008000U );
264280
265- for (i = 1024U ;
266- (0x100U & aq_hw_read_reg (self , 0x00000200U )) && -- i ;) {
267- }
281+ if (IS_CHIP_FEATURE (REVISION_B1 ))
282+ AQ_HW_WAIT_FOR (a != aq_hw_read_reg (self ,
283+ HW_ATL_MIF_ADDR ),
284+ 1 , 1000U );
285+ else
286+ AQ_HW_WAIT_FOR (!(0x100 & aq_hw_read_reg (self ,
287+ HW_ATL_MIF_CMD )),
288+ 1 , 1000U );
268289
269- * (p ++ ) = aq_hw_read_reg (self , 0x0000020CU );
290+ * (p ++ ) = aq_hw_read_reg (self , HW_ATL_MIF_VAL );
291+ a += 4 ;
270292 }
271293
272294 hw_atl_reg_glb_cpu_sem_set (self , 1U , HW_ATL_FW_SM_RAM );
@@ -662,14 +684,18 @@ void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p)
662684 u32 val = hw_atl_reg_glb_mif_id_get (self );
663685 u32 mif_rev = val & 0xFFU ;
664686
665- if ((3U & mif_rev ) == 1U ) {
666- chip_features |=
667- HAL_ATLANTIC_UTILS_CHIP_REVISION_A0 |
687+ if ((0xFU & mif_rev ) == 1U ) {
688+ chip_features |= HAL_ATLANTIC_UTILS_CHIP_REVISION_A0 |
668689 HAL_ATLANTIC_UTILS_CHIP_MPI_AQ |
669690 HAL_ATLANTIC_UTILS_CHIP_MIPS ;
670- } else if ((3U & mif_rev ) == 2U ) {
671- chip_features |=
672- HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 |
691+ } else if ((0xFU & mif_rev ) == 2U ) {
692+ chip_features |= HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 |
693+ HAL_ATLANTIC_UTILS_CHIP_MPI_AQ |
694+ HAL_ATLANTIC_UTILS_CHIP_MIPS |
695+ HAL_ATLANTIC_UTILS_CHIP_TPO2 |
696+ HAL_ATLANTIC_UTILS_CHIP_RPF2 ;
697+ } else if ((0xFU & mif_rev ) == 0xAU ) {
698+ chip_features |= HAL_ATLANTIC_UTILS_CHIP_REVISION_B1 |
673699 HAL_ATLANTIC_UTILS_CHIP_MPI_AQ |
674700 HAL_ATLANTIC_UTILS_CHIP_MIPS |
675701 HAL_ATLANTIC_UTILS_CHIP_TPO2 |
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