@@ -3315,97 +3315,6 @@ void MacroAssembler::reinit_heapbase()
33153315 }
33163316}
33173317
3318- // this simulates the behaviour of the x86 cmpxchg instruction using a
3319- // load linked/store conditional pair. we use the acquire/release
3320- // versions of these instructions so that we flush pending writes as
3321- // per Java semantics.
3322-
3323- // n.b the x86 version assumes the old value to be compared against is
3324- // in rax and updates rax with the value located in memory if the
3325- // cmpxchg fails. we supply a register for the old value explicitly
3326-
3327- // the aarch64 load linked/store conditional instructions do not
3328- // accept an offset. so, unlike x86, we must provide a plain register
3329- // to identify the memory word to be compared/exchanged rather than a
3330- // register+offset Address.
3331-
3332- void MacroAssembler::cmpxchgptr (Register oldv, Register newv, Register addr, Register tmp,
3333- Label &succeed, Label *fail) {
3334- // oldv holds comparison value
3335- // newv holds value to write in exchange
3336- // addr identifies memory word to compare against/update
3337- if (UseLSE) {
3338- mov (tmp, oldv);
3339- casal (Assembler::xword, oldv, newv, addr);
3340- cmp (tmp, oldv);
3341- br (Assembler::EQ, succeed);
3342- membar (AnyAny);
3343- } else {
3344- Label retry_load, nope;
3345- prfm (Address (addr), PSTL1STRM);
3346- bind (retry_load);
3347- // flush and load exclusive from the memory location
3348- // and fail if it is not what we expect
3349- ldaxr (tmp, addr);
3350- cmp (tmp, oldv);
3351- br (Assembler::NE, nope);
3352- // if we store+flush with no intervening write tmp will be zero
3353- stlxr (tmp, newv, addr);
3354- cbzw (tmp, succeed);
3355- // retry so we only ever return after a load fails to compare
3356- // ensures we don't return a stale value after a failed write.
3357- b (retry_load);
3358- // if the memory word differs we return it in oldv and signal a fail
3359- bind (nope);
3360- membar (AnyAny);
3361- mov (oldv, tmp);
3362- }
3363- if (fail)
3364- b (*fail);
3365- }
3366-
3367- void MacroAssembler::cmpxchg_obj_header (Register oldv, Register newv, Register obj, Register tmp,
3368- Label &succeed, Label *fail) {
3369- assert (oopDesc::mark_offset_in_bytes () == 0 , " assumption" );
3370- cmpxchgptr (oldv, newv, obj, tmp, succeed, fail);
3371- }
3372-
3373- void MacroAssembler::cmpxchgw (Register oldv, Register newv, Register addr, Register tmp,
3374- Label &succeed, Label *fail) {
3375- // oldv holds comparison value
3376- // newv holds value to write in exchange
3377- // addr identifies memory word to compare against/update
3378- // tmp returns 0/1 for success/failure
3379- if (UseLSE) {
3380- mov (tmp, oldv);
3381- casal (Assembler::word, oldv, newv, addr);
3382- cmp (tmp, oldv);
3383- br (Assembler::EQ, succeed);
3384- membar (AnyAny);
3385- } else {
3386- Label retry_load, nope;
3387- prfm (Address (addr), PSTL1STRM);
3388- bind (retry_load);
3389- // flush and load exclusive from the memory location
3390- // and fail if it is not what we expect
3391- ldaxrw (tmp, addr);
3392- cmp (tmp, oldv);
3393- br (Assembler::NE, nope);
3394- // if we store+flush with no intervening write tmp will be zero
3395- stlxrw (tmp, newv, addr);
3396- cbzw (tmp, succeed);
3397- // retry so we only ever return after a load fails to compare
3398- // ensures we don't return a stale value after a failed write.
3399- b (retry_load);
3400- // if the memory word differs we return it in oldv and signal a fail
3401- bind (nope);
3402- membar (AnyAny);
3403- mov (oldv, tmp);
3404- }
3405- if (fail)
3406- b (*fail);
3407- }
3408-
34093318// A generic CAS; success or failure is in the EQ flag. A weak CAS
34103319// doesn't retry and may fail spuriously. If the oldval is wanted,
34113320// Pass a register for the result, otherwise pass noreg.
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