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| 1 | +; RUN: %dxopt %s -dxil-annotate-with-virtual-regs -hlsl-dxil-debug-instrumentation -S | FileCheck %s |
| 2 | + |
| 3 | +; Expect an i25 cast, or this test isn't testing anything: |
| 4 | +; CHECK: [[CAST:%.*]] = trunc i32 %{{.*}} to i25 |
| 5 | +; |
| 6 | +; Check that we correctly z-extended that i25 before trying to write it to i32 |
| 7 | +; [[ZEXT:%.*]] = zext i25 [[CAST]] to i32 |
| 8 | +; call void @dx.op.bufferStore.i32(i32 69, %dx.types.Handle %PIX_DebugUAV_Handle, i32 %{{.*}}, i32 undef, i32 [[ZEXT]] |
| 9 | + |
| 10 | +; GENERATED FROM: |
| 11 | +; dxc -Emain -Tps_6_1 |
| 12 | + |
| 13 | +; uint param; |
| 14 | +; |
| 15 | +; bool fn() |
| 16 | +; { |
| 17 | +; switch (param) |
| 18 | +; { |
| 19 | +; case 0: |
| 20 | +; case 20: |
| 21 | +; case 24: |
| 22 | +; return false; |
| 23 | +; } |
| 24 | +; return true; |
| 25 | +; } |
| 26 | +; |
| 27 | +; float4 main() : SV_Target |
| 28 | +; { |
| 29 | +; float4 ret = float4(0, 0, 0, 0); |
| 30 | +; if (fn()) |
| 31 | +; { |
| 32 | +; ret = float4(1, 1, 1, 1); |
| 33 | +; } |
| 34 | +; return ret; |
| 35 | +; } |
| 36 | + |
| 37 | + |
| 38 | + |
| 39 | +target datalayout = "e-m:e-p:32:32-i1:32-i8:32-i16:32-i32:32-i64:64-f16:32-f32:32-f64:64-n8:16:32:64" |
| 40 | +target triple = "dxil-ms-dx" |
| 41 | + |
| 42 | +%dx.types.Handle = type { i8* } |
| 43 | +%dx.types.CBufRet.i32 = type { i32, i32, i32, i32 } |
| 44 | +%"$Globals" = type { i32 } |
| 45 | + |
| 46 | +define void @main() { |
| 47 | + %1 = call %dx.types.Handle @dx.op.createHandle(i32 57, i8 2, i32 0, i32 0, i1 false) ; CreateHandle(resourceClass,rangeId,index,nonUniformIndex) |
| 48 | + %2 = call %dx.types.CBufRet.i32 @dx.op.cbufferLoadLegacy.i32(i32 59, %dx.types.Handle %1, i32 0) ; CBufferLoadLegacy(handle,regIndex) |
| 49 | + %3 = extractvalue %dx.types.CBufRet.i32 %2, 0 |
| 50 | + %4 = icmp ult i32 %3, 25 |
| 51 | + br i1 %4, label %5, label %11 |
| 52 | + |
| 53 | +; <label>:5 ; preds = %0 |
| 54 | + %6 = trunc i32 %3 to i25 |
| 55 | + %7 = lshr i25 15728638, %6 |
| 56 | + %8 = and i25 %7, 1 |
| 57 | + %9 = icmp ne i25 %8, 0 |
| 58 | + %10 = select i1 %9, float 1.000000e+00, float 0.000000e+00 |
| 59 | + br label %11 |
| 60 | + |
| 61 | +; <label>:11 ; preds = %5, %0 |
| 62 | + %12 = phi float [ %10, %5 ], [ 1.000000e+00, %0 ] |
| 63 | + call void @dx.op.storeOutput.f32(i32 5, i32 0, i32 0, i8 0, float %12) ; StoreOutput(outputSigId,rowIndex,colIndex,value) |
| 64 | + call void @dx.op.storeOutput.f32(i32 5, i32 0, i32 0, i8 1, float %12) ; StoreOutput(outputSigId,rowIndex,colIndex,value) |
| 65 | + call void @dx.op.storeOutput.f32(i32 5, i32 0, i32 0, i8 2, float %12) ; StoreOutput(outputSigId,rowIndex,colIndex,value) |
| 66 | + call void @dx.op.storeOutput.f32(i32 5, i32 0, i32 0, i8 3, float %12) ; StoreOutput(outputSigId,rowIndex,colIndex,value) |
| 67 | + ret void |
| 68 | +} |
| 69 | + |
| 70 | +; Function Attrs: nounwind |
| 71 | +declare void @dx.op.storeOutput.f32(i32, i32, i32, i8, float) #0 |
| 72 | + |
| 73 | +; Function Attrs: nounwind readonly |
| 74 | +declare %dx.types.CBufRet.i32 @dx.op.cbufferLoadLegacy.i32(i32, %dx.types.Handle, i32) #1 |
| 75 | + |
| 76 | +; Function Attrs: nounwind readonly |
| 77 | +declare %dx.types.Handle @dx.op.createHandle(i32, i8, i32, i32, i1) #1 |
| 78 | + |
| 79 | +attributes #0 = { nounwind } |
| 80 | +attributes #1 = { nounwind readonly } |
| 81 | + |
| 82 | +!llvm.ident = !{!0} |
| 83 | +!dx.version = !{!1} |
| 84 | +!dx.valver = !{!2} |
| 85 | +!dx.shaderModel = !{!3} |
| 86 | +!dx.resources = !{!4} |
| 87 | +!dx.viewIdState = !{!7} |
| 88 | +!dx.entryPoints = !{!8} |
| 89 | + |
| 90 | +!0 = !{!"dxc(private) 1.8.0.4522 (PIX_InputSigValues, 313ba88f3)"} |
| 91 | +!1 = !{i32 1, i32 1} |
| 92 | +!2 = !{i32 1, i32 8} |
| 93 | +!3 = !{!"ps", i32 6, i32 1} |
| 94 | +!4 = !{null, null, !5, null} |
| 95 | +!5 = !{!6} |
| 96 | +!6 = !{i32 0, %"$Globals"* undef, !"", i32 0, i32 0, i32 1, i32 4, null} |
| 97 | +!7 = !{[2 x i32] [i32 0, i32 4]} |
| 98 | +!8 = !{void ()* @main, !"main", !9, !4, null} |
| 99 | +!9 = !{null, !10, null} |
| 100 | +!10 = !{!11} |
| 101 | +!11 = !{i32 0, !"SV_Target", i8 9, i8 16, !12, i8 0, i32 1, i8 4, i32 0, i8 0, !13} |
| 102 | +!12 = !{i32 0} |
| 103 | +!13 = !{i32 3, i32 15} |
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