rebase

Author: kvp

llvm/test/CodeGen/RISCV/div_minsize.ll

@@ -72,38 +72,34 @@ define i32 @testsize4(i32 %x) minsize nounwind {
 define i128 @i128_sdiv(i128 %arg0) minsize nounwind {
 ; RV32IM-LABEL: i128_sdiv:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    addi sp, sp, -64
-; RV32IM-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
-; RV32IM-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
-; RV32IM-NEXT:    lw a3, 0(a1)
-; RV32IM-NEXT:    lw a4, 4(a1)
-; RV32IM-NEXT:    lw a5, 8(a1)
-; RV32IM-NEXT:    lw a6, 12(a1)
-; RV32IM-NEXT:    mv s0, a0
-; RV32IM-NEXT:    li a7, 4
-; RV32IM-NEXT:    addi a0, sp, 40
-; RV32IM-NEXT:    addi a1, sp, 24
-; RV32IM-NEXT:    addi a2, sp, 8
-; RV32IM-NEXT:    sw a7, 8(sp)
-; RV32IM-NEXT:    sw zero, 12(sp)
-; RV32IM-NEXT:    sw zero, 16(sp)
-; RV32IM-NEXT:    sw zero, 20(sp)
-; RV32IM-NEXT:    sw a3, 24(sp)
-; RV32IM-NEXT:    sw a4, 28(sp)
-; RV32IM-NEXT:    sw a5, 32(sp)
-; RV32IM-NEXT:    sw a6, 36(sp)
-; RV32IM-NEXT:    call __divti3
-; RV32IM-NEXT:    lw a0, 40(sp)
-; RV32IM-NEXT:    lw a1, 44(sp)
-; RV32IM-NEXT:    lw a2, 48(sp)
-; RV32IM-NEXT:    lw a3, 52(sp)
-; RV32IM-NEXT:    sw a0, 0(s0)
-; RV32IM-NEXT:    sw a1, 4(s0)
-; RV32IM-NEXT:    sw a2, 8(s0)
-; RV32IM-NEXT:    sw a3, 12(s0)
-; RV32IM-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
-; RV32IM-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
-; RV32IM-NEXT:    addi sp, sp, 64
+; RV32IM-NEXT:    lw a2, 12(a1)
+; RV32IM-NEXT:    lw a3, 8(a1)
+; RV32IM-NEXT:    lw a4, 0(a1)
+; RV32IM-NEXT:    lw a1, 4(a1)
+; RV32IM-NEXT:    srai a5, a2, 31
+; RV32IM-NEXT:    srli a5, a5, 30
+; RV32IM-NEXT:    add a5, a4, a5
+; RV32IM-NEXT:    sltu a4, a5, a4
+; RV32IM-NEXT:    srli a5, a5, 2
+; RV32IM-NEXT:    add a6, a1, a4
+; RV32IM-NEXT:    sltu a1, a6, a1
+; RV32IM-NEXT:    and a1, a4, a1
+; RV32IM-NEXT:    srli a4, a6, 2
+; RV32IM-NEXT:    slli a6, a6, 30
+; RV32IM-NEXT:    or a5, a5, a6
+; RV32IM-NEXT:    add a1, a3, a1
+; RV32IM-NEXT:    srli a6, a1, 2
+; RV32IM-NEXT:    sltu a3, a1, a3
+; RV32IM-NEXT:    slli a1, a1, 30
+; RV32IM-NEXT:    add a2, a2, a3
+; RV32IM-NEXT:    or a1, a4, a1
+; RV32IM-NEXT:    slli a3, a2, 30
+; RV32IM-NEXT:    srai a2, a2, 2
+; RV32IM-NEXT:    or a3, a6, a3
+; RV32IM-NEXT:    sw a5, 0(a0)
+; RV32IM-NEXT:    sw a1, 4(a0)
+; RV32IM-NEXT:    sw a3, 8(a0)
+; RV32IM-NEXT:    sw a2, 12(a0)
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: i128_sdiv: