Commit 6387c82
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[llvm] Comment on validity of volatile ops on null
Some hardware (for example, certain AVR chips) have peripheral
registers mapped to the data space address 0. Although a volatile
load/store on `ptr null` already generates expected code, the wording
in the LangRef makes operations on null seem like undefined behavior in
all cases. This commit adds a comment that for volatile operations, it
may be defined behavior to access the address null, if the architecture
permits it. The intended use case is MMIO registers with hard-coded
addresses that include bit-value 0. A simple CodeGen test is included
for AVR, as an architecture known to have this quirk, that does `load
volatile` and `store volatile` to `ptr null`, expecting to generate `lds
<reg>, 0` and `sts 0, <reg>`.1 parent e4d21ae commit 6387c82
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