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[ARM] Remove duplicate custom SDag node (NFCI) (#93419)
ARMISD::SUBS is a duplicate of ARMISD::SUBC. The node was introduced in 5745b6a. This patch replaces SUBS with SUBC and reverts changes in *.td files.
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5 files changed

+9
-32
lines changed

5 files changed

+9
-32
lines changed

‎llvm/lib/Target/ARM/ARMISelLowering.cpp‎

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1715,7 +1715,6 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
17151715
MAKE_CASE(ARMISD::BCC_i64)
17161716
MAKE_CASE(ARMISD::FMSTAT)
17171717
MAKE_CASE(ARMISD::CMOV)
1718-
MAKE_CASE(ARMISD::SUBS)
17191718
MAKE_CASE(ARMISD::SSAT)
17201719
MAKE_CASE(ARMISD::USAT)
17211720
MAKE_CASE(ARMISD::ASRL)
@@ -18475,9 +18474,9 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
1847518474
} else if (CC == ARMCC::NE && !isNullConstant(RHS) &&
1847618475
(!Subtarget->isThumb1Only() || isPowerOf2Constant(TrueVal))) {
1847718476
// This seems pointless but will allow us to combine it further below.
18478-
// CMOV 0, z, !=, (CMPZ x, y) -> CMOV (SUBS x, y), z, !=, (SUBS x, y):1
18477+
// CMOV 0, z, !=, (CMPZ x, y) -> CMOV (SUBC x, y), z, !=, (SUBC x, y):1
1847918478
SDValue Sub =
18480-
DAG.getNode(ARMISD::SUBS, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS);
18479+
DAG.getNode(ARMISD::SUBC, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS);
1848118480
SDValue CPSRGlue = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
1848218481
Sub.getValue(1), SDValue());
1848318482
Res = DAG.getNode(ARMISD::CMOV, dl, VT, Sub, TrueVal, ARMcc,
@@ -18489,9 +18488,9 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
1848918488
(!Subtarget->isThumb1Only() || isPowerOf2Constant(FalseVal))) {
1849018489
// This seems pointless but will allow us to combine it further below
1849118490
// Note that we change == for != as this is the dual for the case above.
18492-
// CMOV z, 0, ==, (CMPZ x, y) -> CMOV (SUBS x, y), z, !=, (SUBS x, y):1
18491+
// CMOV z, 0, ==, (CMPZ x, y) -> CMOV (SUBC x, y), z, !=, (SUBC x, y):1
1849318492
SDValue Sub =
18494-
DAG.getNode(ARMISD::SUBS, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS);
18493+
DAG.getNode(ARMISD::SUBC, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS);
1849518494
SDValue CPSRGlue = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
1849618495
Sub.getValue(1), SDValue());
1849718496
Res = DAG.getNode(ARMISD::CMOV, dl, VT, Sub, FalseVal,
@@ -18503,21 +18502,21 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
1850318502

1850418503
// On Thumb1, the DAG above may be further combined if z is a power of 2
1850518504
// (z == 2 ^ K).
18506-
// CMOV (SUBS x, y), z, !=, (SUBS x, y):1 ->
18505+
// CMOV (SUBC x, y), z, !=, (SUBC x, y):1 ->
1850718506
// t1 = (USUBO (SUB x, y), 1)
1850818507
// t2 = (USUBO_CARRY (SUB x, y), t1:0, t1:1)
1850918508
// Result = if K != 0 then (SHL t2:0, K) else t2:0
1851018509
//
1851118510
// This also handles the special case of comparing against zero; it's
18512-
// essentially, the same pattern, except there's no SUBS:
18511+
// essentially, the same pattern, except there's no SUBC:
1851318512
// CMOV x, z, !=, (CMPZ x, 0) ->
1851418513
// t1 = (USUBO x, 1)
1851518514
// t2 = (USUBO_CARRY x, t1:0, t1:1)
1851618515
// Result = if K != 0 then (SHL t2:0, K) else t2:0
1851718516
const APInt *TrueConst;
1851818517
if (Subtarget->isThumb1Only() && CC == ARMCC::NE &&
18519-
((FalseVal.getOpcode() == ARMISD::SUBS &&
18520-
FalseVal.getOperand(0) == LHS && FalseVal.getOperand(1) == RHS) ||
18518+
((FalseVal.getOpcode() == ARMISD::SUBC && FalseVal.getOperand(0) == LHS &&
18519+
FalseVal.getOperand(1) == RHS) ||
1852118520
(FalseVal == LHS && isNullConstant(RHS))) &&
1852218521
(TrueConst = isPowerOf2Constant(TrueVal))) {
1852318522
SDVTList VTs = DAG.getVTList(VT, MVT::i32);

‎llvm/lib/Target/ARM/ARMISelLowering.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,6 @@ class VectorType;
9595
FMSTAT, // ARM fmstat instruction.
9696

9797
CMOV, // ARM conditional move instructions.
98-
SUBS, // Flag-setting subtraction.
9998

10099
SSAT, // Signed saturation
101100
USAT, // Unsigned saturation
@@ -244,7 +243,7 @@ class VectorType;
244243
VADDLVAps, // Same as VADDLVp[su] but with a v4i1 predicate mask
245244
VADDLVApu,
246245
VMLAVs, // sign- or zero-extend the elements of two vectors to i32, multiply
247-
VMLAVu, // them and add the results together, returning an i32 of their sum
246+
VMLAVu, // them and add the results together, returning an i32 of the sum
248247
VMLAVps, // Same as VMLAV[su] with a v4i1 predicate mask
249248
VMLAVpu,
250249
VMLALVs, // Same as VMLAV but with i64, returning the low and

‎llvm/lib/Target/ARM/ARMInstrInfo.td‎

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -160,7 +160,6 @@ def ARMintretglue : SDNode<"ARMISD::INTRET_GLUE", SDT_ARMcall,
160160
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
161161
def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
162162
[SDNPInGlue]>;
163-
def ARMsubs : SDNode<"ARMISD::SUBS", SDTIntBinOp, [SDNPOutGlue]>;
164163

165164
def ARMssat : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>;
166165

@@ -3879,14 +3878,6 @@ let isAdd = 1 in
38793878
defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>;
38803879
defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>;
38813880

3882-
def : ARMPat<(ARMsubs GPR:$Rn, mod_imm:$imm), (SUBSri $Rn, mod_imm:$imm)>;
3883-
def : ARMPat<(ARMsubs GPR:$Rn, GPR:$Rm), (SUBSrr $Rn, $Rm)>;
3884-
def : ARMPat<(ARMsubs GPR:$Rn, so_reg_imm:$shift),
3885-
(SUBSrsi $Rn, so_reg_imm:$shift)>;
3886-
def : ARMPat<(ARMsubs GPR:$Rn, so_reg_reg:$shift),
3887-
(SUBSrsr $Rn, so_reg_reg:$shift)>;
3888-
3889-
38903881
let isAdd = 1 in
38913882
defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>;
38923883
defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>;

‎llvm/lib/Target/ARM/ARMInstrThumb.td‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1400,12 +1400,6 @@ let hasPostISelHook = 1, Defs = [CPSR] in {
14001400
Sched<[WriteALU]>;
14011401
}
14021402

1403-
1404-
def : T1Pat<(ARMsubs tGPR:$Rn, tGPR:$Rm), (tSUBSrr $Rn, $Rm)>;
1405-
def : T1Pat<(ARMsubs tGPR:$Rn, imm0_7:$imm3), (tSUBSi3 $Rn, imm0_7:$imm3)>;
1406-
def : T1Pat<(ARMsubs tGPR:$Rn, imm0_255:$imm8), (tSUBSi8 $Rn, imm0_255:$imm8)>;
1407-
1408-
14091403
// Sign-extend byte
14101404
def tSXTB : // A8.6.222
14111405
T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),

‎llvm/lib/Target/ARM/ARMInstrThumb2.td‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2438,12 +2438,6 @@ defm t2SUB : T2I_bin_ii12rs<0b101, "sub", sub>;
24382438
defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMaddc, 1>;
24392439
defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMsubc>;
24402440

2441-
def : T2Pat<(ARMsubs GPRnopc:$Rn, t2_so_imm:$imm),
2442-
(t2SUBSri $Rn, t2_so_imm:$imm)>;
2443-
def : T2Pat<(ARMsubs GPRnopc:$Rn, rGPR:$Rm), (t2SUBSrr $Rn, $Rm)>;
2444-
def : T2Pat<(ARMsubs GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
2445-
(t2SUBSrs $Rn, t2_so_reg:$ShiftedRm)>;
2446-
24472441
defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", ARMadde, 1, 1>;
24482442
defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", ARMsube, 0, 1>;
24492443

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