Merge pull request ARMmbed#28 from yennster/uart-debug

Re-added UART clock enable

Author: Jenny Plunkett

targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralNames.h

@@ -54,7 +54,8 @@ typedef enum {
 #define STDIO_UART_RX     USBRX
 #define STDIO_UART        UART_0
 
-#define MBED_UART0        USBTX, USBRX
+#define MBED_UART0        P55, P57
+#define MBED_UART1        P07, P08
 #define MBED_UARTUSB      USBTX, USBRX
 
 #ifdef __cplusplus

targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF.h

@@ -172,14 +172,13 @@ typedef struct
   __IO uint32_t MIS;            /*!< Masked Interrupt Status ,          Address offset : 0x40 */
   __O  uint32_t ICR;            /*!< Interrupt Clear,                   Address offset : 0x44 */
   __IO uint32_t DMACTL;         /*!< DMA Control,                       Address offset : 0x48 */
-  //uint32_t RESERVED1[6];
-  //__IO uint32_t LCTL;           /*!<                                    Address offset : 0x90 */
-  //__IO uint32_t LSS;            /*!<                                    Address offset : 0x94 */
-  //__IO uint32_t LTIM;           /*!<                                    Address offset : 0x98 */
-  //__IO uint32_t 9BITADDR;       /*!<                                    Address offset : 0xA4 */
-  //__IO uint32_t 9BITMASK;       /*!<                                    Address offset : 0xA8 */
-  //__IO uint32_t PP;             /*!<                                    Address offset : 0xFC0 */
-  //__IO uint32_t CC;             /*!<                                    Address offset : 0xFC8 */
+  __IO uint32_t LCTL;           /*!<                                    Address offset : 0x90 */
+  __IO uint32_t LSS;            /*!<                                    Address offset : 0x94 */
+  __IO uint32_t LTIM;           /*!<                                    Address offset : 0x98 */
+  __IO uint32_t BITADDR;        /*!< 9BITADDR                           Address offset : 0xA4 */
+  __IO uint32_t BITMASK;        /*!< 9BITMASK                           Address offset : 0xA8 */
+  __IO uint32_t PP;             /*!<                                    Address offset : 0xFC0 */
+  __IO uint32_t CC;             /*!<                                    Address offset : 0xFC8 */
 } CC3220SF_UART_TypeDef;
 
 

targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_api.c

@@ -149,16 +149,18 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
                 obj->index = 0;
                 obj->baseAddr = CC3220SF_UARTA0_BASE;
                 obj->powerMgrId = 12; /*!< Resource ID: UART 0 */
-                obj->intNum = INT_UARTA0;
+                obj->intNum = INT_UARTA0_IRQn;
                 obj->peripheralId = PRCM_UARTA0;
+                MAP_PRCMPeripheralClkEnable(PRCM_UARTA0, PRCM_RUN_MODE_CLK);
             }
             break;
         case UART_1: {
                 obj->index = 1;
                 obj->baseAddr = CC3220SF_UARTA1_BASE;
                 obj->powerMgrId = 13; /*!< Resource ID: UART 1 */
-                obj->intNum = INT_UARTA1;
+                obj->intNum = INT_UARTA1_IRQn;
                 obj->peripheralId = PRCM_UARTA1;
+                MAP_PRCMPeripheralClkEnable(PRCM_UARTA1, PRCM_RUN_MODE_CLK);
             }
             break;
     }
@@ -247,6 +249,24 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b
 /******************************************************************************
  * INTERRUPTS HANDLING
  ******************************************************************************/
+static inline void uart_irq(uint32_t iir, uint32_t index, CC3220SF_UART_TypeDef *puart) {
+    SerialIrq irq_type;
+    switch(iir) {
+        case 1: irq_type = TxIrq; break;
+        case 2: irq_type = RxIrq; break;
+        default: return;
+    }
+}
+
+void uart0_irq() {
+    int status = MAP_UARTIntStatus(CC3220SF_UARTA0_BASE, false);
+    uart_irq(status, 0, (CC3220SF_UART_TypeDef *)CC3220SF_UART0);
+}
+void uart1_irq() {
+    int status = MAP_UARTIntStatus(CC3220SF_UARTA1_BASE, false);
+    uart_irq(status, 1, (CC3220SF_UART_TypeDef *)CC3220SF_UART1);
+}
+
 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
     irq_handler = handler;
     uart_data[obj->index].serial_irq_id = id;
@@ -255,14 +275,10 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
 static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
     // TODO
     IRQn_Type irq_n = (IRQn_Type)0;
-    //uint32_t vector = 0;
+    uint32_t vector = 0;
     switch ((int)obj->uart) {
-        case UART_0:
-            irq_n = INT_UARTA0_IRQn;
-            break;
-        case UART_1:
-            irq_n = INT_UARTA1_IRQn;
-            break;
+        case UART_0: irq_n = INT_UARTA0_IRQn; vector = (uint32_t)&uart0_irq; break;
+        case UART_1: irq_n = INT_UARTA1_IRQn; vector = (uint32_t)&uart1_irq; break;
     }
 }
 
@@ -322,6 +338,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
     // Check type(s) of flow control to use
     UARTName uart_rts = (UARTName)pinmap_find_peripheral(rxflow, PinMap_UART_RTS);
     UARTName uart_cts = (UARTName)pinmap_find_peripheral(txflow, PinMap_UART_CTS);
+    if(type != FlowControlNone) MBED_ASSERT((int)uart_rts != NC || (int)uart_cts != NC);
 
     switch(type) {
         case FlowControlRTS: