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| 1 | +#include "tlv320dac3100.h" |
| 2 | + |
| 3 | +static i2c_bus_handle_t i2c_handle = NULL; |
| 4 | +static int address = TLV320DAC3100_ADDR; |
| 5 | + |
| 6 | +#define TLV_ASSERT(a, format, b, ...) \ |
| 7 | + if ((a) != 0) { \ |
| 8 | + AD_LOGE(format, ##__VA_ARGS__); \ |
| 9 | + return b; \ |
| 10 | + } |
| 11 | + |
| 12 | +static error_t tlv_write_reg(uint8_t slave_addr, uint8_t reg_add, uint8_t data) { |
| 13 | + return i2c_bus_write_bytes(i2c_handle, slave_addr, ®_add, sizeof(reg_add), |
| 14 | + &data, sizeof(data)); |
| 15 | +} |
| 16 | + |
| 17 | +static error_t tlv_read_reg(uint8_t reg_add, uint8_t *p_data) { |
| 18 | + return i2c_bus_read_bytes(i2c_handle, address, ®_add, sizeof(reg_add), |
| 19 | + p_data, 1); |
| 20 | +} |
| 21 | + |
| 22 | +static error_t tlv_set_page(uint8_t page) { |
| 23 | + return tlv_write_reg(address, TLV320DAC3100_REG_PAGE_SELECT, page); |
| 24 | +} |
| 25 | + |
| 26 | +error_t tlv320dac3100_init(codec_config_t *cfg, i2c_bus_handle_t handle, int addr) { |
| 27 | + AD_LOGI("TLV320DAC3100 start init"); |
| 28 | + |
| 29 | + AD_TRACED(); |
| 30 | + i2c_handle = handle; |
| 31 | + if (addr > 0) address = addr; |
| 32 | + |
| 33 | + // 0. Reset the codec |
| 34 | + AD_LOGI("Resetting codec"); |
| 35 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_RESET, 0x01), "Failed to reset codec", RESULT_FAIL); |
| 36 | + delay(100); // Increased delay to match working sketch |
| 37 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_RESET, 0x00), "Failed to reset codec", RESULT_FAIL); |
| 38 | + delay(10); // Additional delay after reset |
| 39 | + |
| 40 | + // 1. Interface Control - Set codec interface (I2S, 16-bit) |
| 41 | + AD_LOGI("Configuring codec interface"); |
| 42 | + TLV_ASSERT(tlv_set_page(0), "Failed to set page 0", RESULT_FAIL); |
| 43 | + uint8_t if_ctrl = (TLV320DAC3100_FORMAT_I2S << 6) | (TLV320DAC3100_DATA_LEN_16 << 4); |
| 44 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_CODEC_IF_CTRL1, if_ctrl), "Failed to configure I2S interface", RESULT_FAIL); |
| 45 | + |
| 46 | + // 2. Clock MUX and PLL settings |
| 47 | + AD_LOGI("Configuring clocks and PLL"); |
| 48 | + // 2.1 Set codec clock input to PLL and PLL clock input to BCLK |
| 49 | + uint8_t clock_mux = (TLV320DAC3100_PLL_CLKIN_BCLK << 2) | TLV320DAC3100_CODEC_CLKIN_PLL; |
| 50 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_CLOCK_MUX1, clock_mux), "Failed to configure clock sources", RESULT_FAIL); |
| 51 | + |
| 52 | + // 2.2 Set PLL values: P=1, R=2, J=32, D=0 (matching working sketch) |
| 53 | + uint8_t pll_pr = (1 << 4) | 2; // P=1, R=2 |
| 54 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_PLL_PROG_PR, pll_pr), "Failed to set PLL P&R", RESULT_FAIL); |
| 55 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_PLL_PROG_J, 32), "Failed to set PLL J", RESULT_FAIL); |
| 56 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_PLL_PROG_D_MSB, 0x00), "Failed to set PLL D MSB", RESULT_FAIL); |
| 57 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_PLL_PROG_D_LSB, 0x00), "Failed to set PLL D LSB", RESULT_FAIL); |
| 58 | + |
| 59 | + // 3. DAC/ADC config |
| 60 | + AD_LOGI("Configuring DAC dividers"); |
| 61 | + // 3.1 Set NDAC = 8 (bit 7 = enable, bits 6:0 = value) |
| 62 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_NDAC, 0x80 | 8), "Failed to set NDAC", RESULT_FAIL); |
| 63 | + |
| 64 | + // 3.2 Set MDAC = 2 (bit 7 = enable, bits 6:0 = value) |
| 65 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_MDAC, 0x80 | 2), "Failed to set MDAC", RESULT_FAIL); |
| 66 | + |
| 67 | + // 4. Power up the PLL (bit 7 = 1 to power up) |
| 68 | + AD_LOGI("Powering up PLL"); |
| 69 | + uint8_t pll_power = 0x80 | pll_pr; // Set power bit (7) and keep P&R values |
| 70 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_PLL_PROG_PR, pll_power), "Failed to power up PLL", RESULT_FAIL); |
| 71 | + |
| 72 | + // 5. DAC Setup |
| 73 | + AD_LOGI("Configuring DAC data path"); |
| 74 | + // 5.1 Set DAC data path (power up both DACs, normal paths, 1 sample volume step) |
| 75 | + uint8_t dac_path = (1 << 7) | // Left DAC power up |
| 76 | + (1 << 6) | // Right DAC power up |
| 77 | + (TLV320DAC3100_DAC_PATH_NORMAL << 4) | // Left path |
| 78 | + (TLV320DAC3100_DAC_PATH_NORMAL << 2) | // Right path |
| 79 | + TLV320DAC3100_VOLUME_STEP_1SAMPLE; // Volume step |
| 80 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_DAC_DATAPATH, dac_path), "Failed to configure DAC data path", RESULT_FAIL); |
| 81 | + |
| 82 | + // 5.2 Configure analog inputs - switch to page 1 |
| 83 | + TLV_ASSERT(tlv_set_page(1), "Failed to set page 1", RESULT_FAIL); |
| 84 | + uint8_t routing = (TLV320DAC3100_DAC_ROUTE_MIXER << 6) | // Left DAC to mixer |
| 85 | + (TLV320DAC3100_DAC_ROUTE_MIXER << 2); // Right DAC to mixer |
| 86 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_OUT_ROUTING, routing), "Failed to configure analog routing", RESULT_FAIL); |
| 87 | + |
| 88 | + // 6. DAC volume control - switch back to page 0 |
| 89 | + AD_LOGI("Configuring DAC volume"); |
| 90 | + TLV_ASSERT(tlv_set_page(0), "Failed to set page 0", RESULT_FAIL); |
| 91 | + // Unmute both channels, independent volume control |
| 92 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_DAC_VOL_CTRL, TLV320DAC3100_VOL_INDEPENDENT), "Failed to configure volume control", RESULT_FAIL); |
| 93 | + |
| 94 | + // Set channel volumes to +0dB (register value 0x01) - matching working sketch |
| 95 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_DAC_LVOL, 0x01), "Failed to set left volume", RESULT_FAIL); |
| 96 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_DAC_RVOL, 0x01), "Failed to set right volume", RESULT_FAIL); |
| 97 | + |
| 98 | + // 7. Headphone and speaker setup - switch to page 1 |
| 99 | + AD_LOGI("Configuring headphone and speaker outputs"); |
| 100 | + TLV_ASSERT(tlv_set_page(1), "Failed to set page 1", RESULT_FAIL); |
| 101 | + |
| 102 | + // 7.1 Configure headphone driver (power up both, 1.35V common mode, no power down on SCD) |
| 103 | + uint8_t hp_ctrl = (1 << 7) | // Left HP power up |
| 104 | + (1 << 6) | // Right HP power up |
| 105 | + (1 << 2) | // Required bit 2 = 1 |
| 106 | + (TLV320DAC3100_HP_COMMON_1_35V << 3); // Common mode voltage |
| 107 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_HP_DRIVERS, hp_ctrl), "Failed to configure headphone drivers", RESULT_FAIL); |
| 108 | + |
| 109 | + // 7.2 Configure HPL PGA (0dB gain, unmute) |
| 110 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_HPL_DRIVER, (0 << 3) | (1 << 2)), "Failed to configure HPL PGA", RESULT_FAIL); |
| 111 | + |
| 112 | + // 7.3 Configure HPR PGA (0dB gain, unmute) |
| 113 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_HPR_DRIVER, (0 << 3) | (1 << 2)), "Failed to configure HPR PGA", RESULT_FAIL); |
| 114 | + |
| 115 | + // 7.4 Set HPL volume (enable routing, volume=1) |
| 116 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_HPL_VOL, 0x80 | 1), "Failed to set HPL volume", RESULT_FAIL); |
| 117 | + |
| 118 | + // 7.5 Set HPR volume (enable routing, volume=1) |
| 119 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_HPR_VOL, 0x80 | 1), "Failed to set HPR volume", RESULT_FAIL); |
| 120 | + |
| 121 | + // 7.6 Enable speaker amplifier |
| 122 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_SPK_AMP, 0x80), "Failed to enable speaker", RESULT_FAIL); |
| 123 | + |
| 124 | + // 7.7 Configure speaker PGA (6dB gain, unmute) |
| 125 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_SPK_DRIVER, (TLV320DAC3100_SPK_GAIN_6DB << 3) | (1 << 2)), "Failed to configure speaker PGA", RESULT_FAIL); |
| 126 | + |
| 127 | + // 7.8 Set speaker volume (enable routing, volume=1) |
| 128 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_SPK_VOL, 0x80 | 1), "Failed to set speaker volume", RESULT_FAIL); |
| 129 | + |
| 130 | + // 8. MICBIAS and headset detection |
| 131 | + AD_LOGI("Configuring MICBIAS and headset detection"); |
| 132 | + // 8.1 Configure MICBIAS (not powered down, always on, AVDD voltage) |
| 133 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_MICBIAS, (1 << 3) | TLV320DAC3100_MICBIAS_AVDD), "Failed to configure MICBIAS", RESULT_FAIL); |
| 134 | + |
| 135 | + // 8.2 Set headset detect - switch to page 0 |
| 136 | + TLV_ASSERT(tlv_set_page(0), "Failed to set page 0", RESULT_FAIL); |
| 137 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_HEADSET_DETECT, 0x80), "Failed to enable headset detection", RESULT_FAIL); |
| 138 | + |
| 139 | + // 8.3 Set INT1 source (headset detect + button press) |
| 140 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_INT1_CTRL, (1 << 7) | (1 << 6)), "Failed to configure INT1", RESULT_FAIL); |
| 141 | + |
| 142 | + // 8.4 Set GPIO1 mode to INT1 |
| 143 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_GPIO1_CTRL, TLV320DAC3100_GPIO1_INT1 << 2), "Failed to configure GPIO1", RESULT_FAIL); |
| 144 | + |
| 145 | + AD_LOGI("TLV320DAC3100 initialized successfully"); |
| 146 | + return RESULT_OK; |
| 147 | +} |
| 148 | + |
| 149 | +error_t tlv320dac3100_deinit(void) { |
| 150 | + AD_TRACED(); |
| 151 | + TLV_ASSERT(tlv_set_page(0), "Failed to set page 0", RESULT_FAIL); |
| 152 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_DAC_DATAPATH, 0x00), "Failed to power down DACs", RESULT_FAIL); |
| 153 | + TLV_ASSERT(tlv_set_page(1), "Failed to set page 1", RESULT_FAIL); |
| 154 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_HP_DRIVERS, 0x00), "Failed to power down HP", RESULT_FAIL); |
| 155 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_SPK_AMP, 0x00), "Failed to power down speaker", RESULT_FAIL); |
| 156 | + return RESULT_OK; |
| 157 | +} |
| 158 | + |
| 159 | +error_t tlv320dac3100_config_i2s(codec_mode_t mode, I2SDefinition *iface) { |
| 160 | + AD_TRACED(); |
| 161 | + TLV_ASSERT(tlv_set_page(0), "Failed to set page 0", RESULT_FAIL); |
| 162 | + |
| 163 | + uint8_t format_bits = TLV320DAC3100_FORMAT_I2S; |
| 164 | + switch (iface->fmt) { |
| 165 | + case I2S_NORMAL: format_bits = TLV320DAC3100_FORMAT_I2S; break; |
| 166 | + case I2S_LEFT: format_bits = TLV320DAC3100_FORMAT_LEFT_JUSTIFIED; break; |
| 167 | + case I2S_RIGHT: format_bits = TLV320DAC3100_FORMAT_RIGHT_JUSTIFIED; break; |
| 168 | + case I2S_DSP: format_bits = TLV320DAC3100_FORMAT_DSP; break; |
| 169 | + default: AD_LOGE("Unsupported I2S format: %d", iface->fmt); return RESULT_FAIL; |
| 170 | + } |
| 171 | + |
| 172 | + uint8_t len_bits = TLV320DAC3100_DATA_LEN_16; |
| 173 | + switch (iface->bits) { |
| 174 | + case BIT_LENGTH_16BITS: len_bits = TLV320DAC3100_DATA_LEN_16; break; |
| 175 | + case BIT_LENGTH_20BITS: len_bits = TLV320DAC3100_DATA_LEN_20; break; |
| 176 | + case BIT_LENGTH_24BITS: len_bits = TLV320DAC3100_DATA_LEN_24; break; |
| 177 | + case BIT_LENGTH_32BITS: len_bits = TLV320DAC3100_DATA_LEN_32; break; |
| 178 | + default: AD_LOGE("Unsupported bit length: %d", iface->bits); return RESULT_FAIL; |
| 179 | + } |
| 180 | + |
| 181 | + uint8_t if_ctrl = (format_bits << 6) | (len_bits << 4); |
| 182 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_CODEC_IF_CTRL1, if_ctrl), "Failed to configure I2S", RESULT_FAIL); |
| 183 | + |
| 184 | + return RESULT_OK; |
| 185 | +} |
| 186 | + |
| 187 | +error_t tlv320dac3100_set_volume(int volume) { |
| 188 | + AD_LOGD("tlv320dac3100_set_volume: %d", volume); |
| 189 | + TLV_ASSERT(tlv_set_page(0), "Failed to set page 0", RESULT_FAIL); |
| 190 | + |
| 191 | + if (volume < 0) volume = 0; |
| 192 | + if (volume > 100) volume = 100; |
| 193 | + |
| 194 | + // Convert 0-100 to dB range (-63.5 to +24 dB) |
| 195 | + float dB; |
| 196 | + if (volume == 0) { |
| 197 | + dB = -63.5f; // Mute |
| 198 | + } else if (volume == 100) { |
| 199 | + dB = 24.0f; // Max volume |
| 200 | + } else { |
| 201 | + // Map 0-100 to -63.5 to +24 dB with better linearity |
| 202 | + dB = -63.5f + (volume * 0.875f); |
| 203 | + } |
| 204 | + |
| 205 | + // Convert dB to register value (2dB steps) with proper bounds |
| 206 | + int8_t reg_val; |
| 207 | + if (dB <= -63.5f) { |
| 208 | + reg_val = -127; // Mute |
| 209 | + } else if (dB >= 24.0f) { |
| 210 | + reg_val = 48; // Max volume |
| 211 | + } else { |
| 212 | + reg_val = (int8_t)(dB * 2.0f); |
| 213 | + } |
| 214 | + |
| 215 | + // Set DAC volume |
| 216 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_DAC_LVOL, reg_val), "Failed to set left volume", RESULT_FAIL); |
| 217 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_DAC_RVOL, reg_val), "Failed to set right volume", RESULT_FAIL); |
| 218 | + |
| 219 | + // Also update headphone and speaker volumes |
| 220 | + TLV_ASSERT(tlv_set_page(1), "Failed to set page 1", RESULT_FAIL); |
| 221 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_HPL_VOL, 0x80 | reg_val), "Failed to set HPL volume", RESULT_FAIL); |
| 222 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_HPR_VOL, 0x80 | reg_val), "Failed to set HPR volume", RESULT_FAIL); |
| 223 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_SPK_VOL, 0x80 | reg_val), "Failed to set speaker volume", RESULT_FAIL); |
| 224 | + |
| 225 | + return RESULT_OK; |
| 226 | +} |
| 227 | + |
| 228 | +error_t tlv320dac3100_get_volume(int *volume) { |
| 229 | + AD_TRACED(); |
| 230 | + TLV_ASSERT(tlv_set_page(0), "Failed to set page 0", RESULT_FAIL); |
| 231 | + |
| 232 | + uint8_t reg_val; |
| 233 | + TLV_ASSERT(tlv_read_reg(TLV320DAC3100_REG_DAC_LVOL, ®_val), "Failed to read volume", RESULT_FAIL); |
| 234 | + |
| 235 | + // Convert register value to dB |
| 236 | + float dB = (int8_t)reg_val * 0.5f; |
| 237 | + |
| 238 | + // Convert dB to 0-100 range |
| 239 | + if (dB <= -63.5f) { |
| 240 | + *volume = 0; |
| 241 | + } else if (dB >= 24.0f) { |
| 242 | + *volume = 100; |
| 243 | + } else { |
| 244 | + *volume = (int)((dB + 63.5f) / 0.875f); |
| 245 | + } |
| 246 | + |
| 247 | + return RESULT_OK; |
| 248 | +} |
| 249 | + |
| 250 | +error_t tlv320dac3100_set_mute(bool enable) { |
| 251 | + AD_TRACED(); |
| 252 | + TLV_ASSERT(tlv_set_page(0), "Failed to set page 0", RESULT_FAIL); |
| 253 | + |
| 254 | + uint8_t vol_ctrl = enable ? 0x0C : 0x00; // Set mute bits for both channels |
| 255 | + TLV_ASSERT(tlv_write_reg(address, TLV320DAC3100_REG_DAC_VOL_CTRL, vol_ctrl), "Failed to set mute", RESULT_FAIL); |
| 256 | + |
| 257 | + return RESULT_OK; |
| 258 | +} |
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