Skip to content

Milestones

List view

  • The idea is to implement a new simulation engine that overcomes some of the limitations of the current simulation engine. The current algorithm has been designed to simulate complete processors at high speed, so that even more complex exercises can be implemented in assembler. To achieve this, a very simple simulation model was developed. The restrictions are: 1. No resistors can be simulated, which means that some CMOS circuits can not be built. 2. There are no real diodes. 3. There are only unidirectional splitters. This limits the development of circuits with 74xx chips, and the construction of complex relay circuits. However, it greatly simplifies the export to verilog and VHDL. The goal is to develop a new engine that overrides the limitations without harming performance. Maybe this new engine will never be implemented.

    No due date
    0/3 issues closed