@@ -1480,7 +1480,9 @@ i2c_err_t i2cDetachSDA(i2c_t * i2c, int8_t sda)
14801480 * */
14811481// 24Nov17 only supports Master Mode
14821482i2c_t * i2cInit (uint8_t i2c_num , int8_t sda , int8_t scl , uint32_t frequency ) {
1483+ #ifdef ENABLE_I2C_DEBUG_BUFFER
14831484 log_v ("num=%d sda=%d scl=%d freq=%d" ,i2c_num , sda , scl , frequency );
1485+ #endif
14841486 if (i2c_num > 1 ) {
14851487 return NULL ;
14861488 }
@@ -1674,8 +1676,9 @@ i2c_err_t i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed)
16741676 clk_speed = apb /(period * 2 );
16751677 log_d ("APB Freq too fast, Increasing i2c Freq to %d Hz" ,clk_speed );
16761678 }
1679+ #ifdef ENABLE_I2C_DEBUG_BUFFER
16771680 log_v ("freq=%dHz" ,clk_speed );
1678-
1681+ #endif
16791682 uint32_t halfPeriod = period /2 ;
16801683 uint32_t quarterPeriod = period /4 ;
16811684
@@ -1689,14 +1692,17 @@ i2c_err_t i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed)
16891692 available when a Fifo interrupt is triggered. This allows enough room in the Fifo so that
16901693 interrupt latency does not cause a Fifo overflow/underflow event.
16911694*/
1695+ #ifdef ENABLE_I2C_DEBUG_BUFFER
16921696 log_v ("cpu Freq=%dMhz, i2c Freq=%dHz" ,getCpuFrequencyMhz (),clk_speed );
1697+ #endif
16931698 uint32_t fifo_delta = (INTERRUPT_CYCLE_OVERHEAD /((getCpuFrequencyMhz ()* 1000000 / clk_speed )* 10 ))+ 1 ;
16941699 if (fifo_delta > 24 ) fifo_delta = 24 ;
16951700 f .rx_fifo_full_thrhd = 32 - fifo_delta ;
16961701 f .tx_fifo_empty_thrhd = fifo_delta ;
16971702 i2c -> dev -> fifo_conf .val = f .val ; // set thresholds
1703+ #ifdef ENABLE_I2C_DEBUG_BUFFER
16981704 log_v ("Fifo delta=%d" ,fifo_delta );
1699-
1705+ #endif
17001706 //the clock num during SCL is low level
17011707 i2c -> dev -> scl_low_period .period = period ;
17021708 //the clock num during SCL is high level
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