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Jason2866me-no-devP-R-O-C-H-Y
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Add ESP32-C2 support (#8881)
* add c2 * Fix typo * changes from code review * rm hack needed to compile for c2 * rm `DARDUINO_USB_MODE=1` not needed for c2 * log_e message no RMT support * correct log_e * Update esp32-hal-rgb-led.c * Add component test build for ESP32-C2 * Disable most components for ESP32-C2 * Add missing ADC SOC defines for ESP32-C2 * Add hidden board definition and fix LED pin in variant * Add default empty zigbee libs and mode * Change SPI default pins * change rx1 tx1 default gpio --------- Co-authored-by: Me No Dev <[email protected]> Co-authored-by: me-no-dev <[email protected]> Co-authored-by: Jan Procházka <[email protected]>
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‎.github/workflows/push.yml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ jobs:
9393
# https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/tools/idf-docker-image.html
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# for details.
9595
idf_ver: ["release-v5.1"]
96-
idf_target: ["esp32", "esp32s2", "esp32s3", "esp32c3", "esp32c6", "esp32h2"]
96+
idf_target: ["esp32", "esp32s2", "esp32s3", "esp32c2", "esp32c3", "esp32c6", "esp32h2"]
9797
container: espressif/idf:${{ matrix.idf_ver }}
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steps:
9999
- name: Check out arduino-esp32 as a component

‎boards.txt‎

Lines changed: 115 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,121 @@ menu.LORAWAN_PREAMBLE_LENGTH=LoRaWan Preamble Length
3030
### DO NOT PUT BOARDS ABOVE THE OFFICIAL ESPRESSIF BOARDS! ###
3131
##############################################################
3232

33+
esp32c2.name=ESP32C2 Dev Module
34+
esp32c2.hide=true
35+
36+
esp32c2.bootloader.tool=esptool_py
37+
esp32c2.bootloader.tool.default=esptool_py
38+
39+
esp32c2.upload.tool=esptool_py
40+
esp32c2.upload.tool.default=esptool_py
41+
esp32c2.upload.tool.network=esp_ota
42+
43+
esp32c2.upload.maximum_size=1310720
44+
esp32c2.upload.maximum_data_size=327680
45+
esp32c2.upload.flags=
46+
esp32c2.upload.extra_flags=
47+
esp32c2.upload.use_1200bps_touch=false
48+
esp32c2.upload.wait_for_upload_port=false
49+
50+
esp32c2.serial.disableDTR=false
51+
esp32c2.serial.disableRTS=false
52+
53+
esp32c2.build.tarch=riscv32
54+
esp32c2.build.target=esp
55+
esp32c2.build.mcu=esp32c2
56+
esp32c2.build.core=esp32
57+
esp32c2.build.variant=esp32c2
58+
esp32c2.build.board=ESP32C2_DEV
59+
esp32c2.build.bootloader_addr=0x0
60+
61+
esp32c2.build.cdc_on_boot=0
62+
esp32c2.build.f_cpu=120000000L
63+
esp32c2.build.flash_size=2MB
64+
esp32c2.build.flash_freq=60m
65+
esp32c2.build.flash_mode=qio
66+
esp32c2.build.boot=qio
67+
esp32c2.build.partitions=minimal
68+
esp32c2.build.defines=
69+
70+
esp32c2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
71+
esp32c2.menu.PartitionScheme.minimal.build.partitions=minimal
72+
esp32c2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
73+
esp32c2.menu.PartitionScheme.default.build.partitions=default
74+
esp32c2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
75+
esp32c2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
76+
esp32c2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
77+
esp32c2.menu.PartitionScheme.no_ota.build.partitions=no_ota
78+
esp32c2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
79+
esp32c2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
80+
esp32c2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
81+
esp32c2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
82+
esp32c2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
83+
esp32c2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
84+
esp32c2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
85+
esp32c2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
86+
esp32c2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
87+
esp32c2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
88+
esp32c2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
89+
esp32c2.menu.PartitionScheme.huge_app.build.partitions=huge_app
90+
esp32c2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
91+
esp32c2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
92+
esp32c2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
93+
esp32c2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
94+
95+
esp32c2.menu.FlashMode.qio=QIO
96+
esp32c2.menu.FlashMode.qio.build.flash_mode=dio
97+
esp32c2.menu.FlashMode.qio.build.boot=qio
98+
esp32c2.menu.FlashMode.dio=DIO
99+
esp32c2.menu.FlashMode.dio.build.flash_mode=dio
100+
esp32c2.menu.FlashMode.dio.build.boot=dio
101+
102+
esp32c2.menu.FlashFreq.60=60MHz
103+
esp32c2.menu.FlashFreq.60.build.flash_freq=60m
104+
esp32c2.menu.FlashFreq.30=30MHz
105+
esp32c2.menu.FlashFreq.30.build.flash_freq=30m
106+
107+
esp32c2.menu.FlashSize.2M=2MB (16Mb)
108+
esp32c2.menu.FlashSize.2M.build.flash_size=2MB
109+
esp32c2.menu.FlashSize.2M.build.partitions=minimal
110+
esp32c2.menu.FlashSize.4M=4MB (32Mb)
111+
esp32c2.menu.FlashSize.4M.build.flash_size=4MB
112+
113+
esp32c2.menu.UploadSpeed.921600=921600
114+
esp32c2.menu.UploadSpeed.921600.upload.speed=921600
115+
esp32c2.menu.UploadSpeed.115200=115200
116+
esp32c2.menu.UploadSpeed.115200.upload.speed=115200
117+
esp32c2.menu.UploadSpeed.256000.windows=256000
118+
esp32c2.menu.UploadSpeed.256000.upload.speed=256000
119+
esp32c2.menu.UploadSpeed.230400.windows.upload.speed=256000
120+
esp32c2.menu.UploadSpeed.230400=230400
121+
esp32c2.menu.UploadSpeed.230400.upload.speed=230400
122+
esp32c2.menu.UploadSpeed.460800.linux=460800
123+
esp32c2.menu.UploadSpeed.460800.macosx=460800
124+
esp32c2.menu.UploadSpeed.460800.upload.speed=460800
125+
esp32c2.menu.UploadSpeed.512000.windows=512000
126+
esp32c2.menu.UploadSpeed.512000.upload.speed=512000
127+
128+
esp32c2.menu.DebugLevel.none=None
129+
esp32c2.menu.DebugLevel.none.build.code_debug=0
130+
esp32c2.menu.DebugLevel.error=Error
131+
esp32c2.menu.DebugLevel.error.build.code_debug=1
132+
esp32c2.menu.DebugLevel.warn=Warn
133+
esp32c2.menu.DebugLevel.warn.build.code_debug=2
134+
esp32c2.menu.DebugLevel.info=Info
135+
esp32c2.menu.DebugLevel.info.build.code_debug=3
136+
esp32c2.menu.DebugLevel.debug=Debug
137+
esp32c2.menu.DebugLevel.debug.build.code_debug=4
138+
esp32c2.menu.DebugLevel.verbose=Verbose
139+
esp32c2.menu.DebugLevel.verbose.build.code_debug=5
140+
141+
esp32c2.menu.EraseFlash.none=Disabled
142+
esp32c2.menu.EraseFlash.none.upload.erase_cmd=
143+
esp32c2.menu.EraseFlash.all=Enabled
144+
esp32c2.menu.EraseFlash.all.upload.erase_cmd=-e
145+
146+
##############################################################
147+
33148
esp32h2.name=ESP32H2 Dev Module
34149
esp32h2.vid.0=0x303a
35150
esp32h2.pid.0=0x1001

‎cores/esp32/Esp.cpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,9 @@ extern "C" {
4848
#include "esp32s3/rom/spi_flash.h"
4949
#include "soc/efuse_reg.h"
5050
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32s3 is located at 0x0000
51+
#elif CONFIG_IDF_TARGET_ESP32C2
52+
#include "esp32c2/rom/spi_flash.h"
53+
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c2 is located at 0x0000
5154
#elif CONFIG_IDF_TARGET_ESP32C3
5255
#include "esp32c3/rom/spi_flash.h"
5356
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c3 is located at 0x0000
@@ -366,7 +369,7 @@ FlashMode_t EspClass::getFlashChipMode(void)
366369
#if CONFIG_IDF_TARGET_ESP32S2
367370
uint32_t spi_ctrl = REG_READ(PERIPHS_SPI_FLASH_CTRL);
368371
#else
369-
#if CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6
372+
#if CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
370373
uint32_t spi_ctrl = REG_READ(DR_REG_SPI0_BASE + 0x8);
371374
#else
372375
uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0));

‎cores/esp32/HardwareSerial.h‎

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Original file line numberDiff line numberDiff line change
@@ -118,6 +118,8 @@ typedef enum {
118118
#define SOC_RX0 (gpio_num_t)3
119119
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
120120
#define SOC_RX0 (gpio_num_t)44
121+
#elif CONFIG_IDF_TARGET_ESP32C2
122+
#define SOC_RX0 (gpio_num_t)19
121123
#elif CONFIG_IDF_TARGET_ESP32C3
122124
#define SOC_RX0 (gpio_num_t)20
123125
#elif CONFIG_IDF_TARGET_ESP32C6
@@ -132,6 +134,8 @@ typedef enum {
132134
#define SOC_TX0 (gpio_num_t)1
133135
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
134136
#define SOC_TX0 (gpio_num_t)43
137+
#elif CONFIG_IDF_TARGET_ESP32C2
138+
#define SOC_TX0 (gpio_num_t)20
135139
#elif CONFIG_IDF_TARGET_ESP32C3
136140
#define SOC_TX0 (gpio_num_t)21
137141
#elif CONFIG_IDF_TARGET_ESP32C6
@@ -149,6 +153,8 @@ typedef enum {
149153
#define RX1 (gpio_num_t)26
150154
#elif CONFIG_IDF_TARGET_ESP32S2
151155
#define RX1 (gpio_num_t)4
156+
#elif CONFIG_IDF_TARGET_ESP32C2
157+
#define RX1 (gpio_num_t)10
152158
#elif CONFIG_IDF_TARGET_ESP32C3
153159
#define RX1 (gpio_num_t)18
154160
#elif CONFIG_IDF_TARGET_ESP32S3
@@ -165,6 +171,8 @@ typedef enum {
165171
#define TX1 (gpio_num_t)27
166172
#elif CONFIG_IDF_TARGET_ESP32S2
167173
#define TX1 (gpio_num_t)5
174+
#elif CONFIG_IDF_TARGET_ESP32C2
175+
#define TX1 (gpio_num_t)18
168176
#elif CONFIG_IDF_TARGET_ESP32C3
169177
#define TX1 (gpio_num_t)19
170178
#elif CONFIG_IDF_TARGET_ESP32S3

‎cores/esp32/esp32-hal-adc.c‎

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Original file line numberDiff line numberDiff line change
@@ -21,6 +21,14 @@
2121
#include "esp_adc/adc_continuous.h"
2222
#include "esp_adc/adc_cali_scheme.h"
2323

24+
// ESP32-C2 does not define those two for some reason
25+
#ifndef SOC_ADC_DIGI_RESULT_BYTES
26+
#define SOC_ADC_DIGI_RESULT_BYTES (4)
27+
#endif
28+
#ifndef SOC_ADC_DIGI_DATA_BYTES_PER_CONV
29+
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
30+
#endif
31+
2432
static uint8_t __analogAttenuation = ADC_11db;
2533
static uint8_t __analogWidth = SOC_ADC_RTC_MAX_BITWIDTH;
2634
static uint8_t __analogReturnedWidth = SOC_ADC_RTC_MAX_BITWIDTH;

‎cores/esp32/esp32-hal-cpu.c‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919
#include "esp_attr.h"
2020
#include "esp_log.h"
2121
#include "soc/rtc.h"
22-
#if !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
22+
#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
2323
#include "soc/rtc_cntl_reg.h"
2424
#include "soc/apb_ctrl_reg.h"
2525
#endif
@@ -38,6 +38,8 @@
3838
#elif CONFIG_IDF_TARGET_ESP32S3
3939
#include "freertos/xtensa_timer.h"
4040
#include "esp32s3/rom/rtc.h"
41+
#elif CONFIG_IDF_TARGET_ESP32C2
42+
#include "esp32c2/rom/rtc.h"
4143
#elif CONFIG_IDF_TARGET_ESP32C3
4244
#include "esp32c3/rom/rtc.h"
4345
#elif CONFIG_IDF_TARGET_ESP32C6
@@ -153,7 +155,7 @@ bool removeApbChangeCallback(void * arg, apb_change_cb_t cb){
153155
}
154156

155157
static uint32_t calculateApb(rtc_cpu_freq_config_t * conf){
156-
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
158+
#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
157159
return APB_CLK_FREQ;
158160
#else
159161
if(conf->freq_mhz >= 80){
@@ -228,7 +230,7 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz){
228230
}
229231
//Make the frequency change
230232
rtc_clk_cpu_freq_set_config_fast(&conf);
231-
#if !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
233+
#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
232234
if(capb != apb){
233235
//Update REF_TICK (uncomment if REF_TICK is different than 1MHz)
234236
//if(conf.freq_mhz < 80){
@@ -241,7 +243,7 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz){
241243
}
242244
#endif
243245
//Update FreeRTOS Tick Divisor
244-
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
246+
#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
245247

246248
#elif CONFIG_IDF_TARGET_ESP32S3
247249

‎cores/esp32/esp32-hal-i2c-slave.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -168,7 +168,7 @@ static inline void i2c_ll_stretch_clr(i2c_dev_t *hw)
168168

169169
static inline bool i2c_ll_slave_addressed(i2c_dev_t *hw)
170170
{
171-
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
171+
#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
172172
return hw->sr.slave_addressed;
173173
#else
174174
return hw->status_reg.slave_addressed;
@@ -177,7 +177,7 @@ static inline bool i2c_ll_slave_addressed(i2c_dev_t *hw)
177177

178178
static inline bool i2c_ll_slave_rw(i2c_dev_t *hw)//not exposed by hal_ll
179179
{
180-
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
180+
#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
181181
return hw->sr.slave_rw;
182182
#else
183183
return hw->status_reg.slave_rw;

‎cores/esp32/esp32-hal-matrix.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,8 @@
2424
#include "esp32s2/rom/gpio.h"
2525
#elif CONFIG_IDF_TARGET_ESP32S3
2626
#include "esp32s3/rom/gpio.h"
27+
#elif CONFIG_IDF_TARGET_ESP32C2
28+
#include "esp32c2/rom/gpio.h"
2729
#elif CONFIG_IDF_TARGET_ESP32C3
2830
#include "esp32c3/rom/gpio.h"
2931
#elif CONFIG_IDF_TARGET_ESP32C6

‎cores/esp32/esp32-hal-misc.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929
#endif //CONFIG_BT_ENABLED
3030
#include <sys/time.h>
3131
#include "soc/rtc.h"
32-
#if !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
32+
#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
3333
#include "soc/rtc_cntl_reg.h"
3434
#include "soc/apb_ctrl_reg.h"
3535
#endif
@@ -45,6 +45,8 @@
4545
#include "esp32s2/rom/rtc.h"
4646
#elif CONFIG_IDF_TARGET_ESP32S3
4747
#include "esp32s3/rom/rtc.h"
48+
#elif CONFIG_IDF_TARGET_ESP32C2
49+
#include "esp32c2/rom/rtc.h"
4850
#elif CONFIG_IDF_TARGET_ESP32C3
4951
#include "esp32c3/rom/rtc.h"
5052
#elif CONFIG_IDF_TARGET_ESP32C6

‎cores/esp32/esp32-hal-rgb-led.c‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,10 @@
1+
#include "soc/soc_caps.h"
2+
13
#include "esp32-hal-rgb-led.h"
24

35

46
void neopixelWrite(uint8_t pin, uint8_t red_val, uint8_t green_val, uint8_t blue_val){
7+
#if SOC_RMT_SUPPORTED
58
rmt_data_t led_data[24];
69

710
// Verify if the pin used is RGB_BUILTIN and fix GPIO number
@@ -34,4 +37,7 @@ void neopixelWrite(uint8_t pin, uint8_t red_val, uint8_t green_val, uint8_t blue
3437
}
3538
}
3639
rmtWrite(pin, led_data, RMT_SYMBOLS_OF(led_data), RMT_WAIT_FOR_EVER);
40+
#else
41+
log_e("RMT is not supported on " CONFIG_IDF_TARGET);
42+
#endif /* SOC_RMT_SUPPORTED */
3743
}

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