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Generate Renode simulation
LiteX provides a script for automatic generation of Renode scripts from the json file containing configuration of the LiteX SoC.
Renode was created by Antmicro as a virtual development tool for multinode embedded networks (both wired and wireless) and is intended to enable a scalable workflow for creating effective, tested and secure IoT systems.
With Renode, developing, testing, debugging and simulating unmodified software for IoT devices is fast, cost-effective and reliable.
For details, see the official webpage.
First, build your LiteX platform with --csr-json csr.json
switch, e.g.:
python3 litex/boards/targets/arty.py --cpu-type vexriscv --with-ethernet --csr-json csr.json
Now, use the generated configuration file as an input for litex_json2renode.py
:
./litex_json2renode.py csr.json \
--resc litex.resc \
--repl litex.repl
--bios-binary soc_ethernetsoc_arty/software/bios/bios.bin
This will generate two files:
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litex.repl
- platform definition file, containing information about all the peripherals and their configuration, -
litex.resc
- Renode script file, allowing to easily run the simulation of the generated platform.
Finally, you can run the simulation by executing the command:
renode litex.resc
The script provides additional options. To discover them and get more informations execute:
./litex_json2renode.py --help
The script can generate the following elements of the LiteX SoC:
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uart
, -
timer0
, -
ethmac
, -
cas
, -
cpu
, -
spiflash
, -
spi
, -
ctrl
, -
i2c0
, -
sdphy
, -
spisdcard
.
Have a question or want to get in touch? Our IRC channel is #litex at irc.libera.chat.
- Welcome to LiteX
- LiteX's internals
- How to
- Create a minimal SoC-TODO
- Add a new Board-TODO
- Add a new Core-WIP
- Add a new CPU-WIP
- Reuse-a-(System)Verilog,-VHDL,-Amaranth,-Spinal-HDL,-Chisel-core
- Use LiteX on the Acorn CLE 215+
- Load application code the CPU(s)
- Use Host Bridges to control/debug a SoC
- Use LiteScope to debug a SoC
- JTAG/GDB Debugging with VexRiscv CPU
- JTAG/GDB Debugging with VexRiscv-SMP, NaxRiscv and VexiiRiscv CPUs
- Document a SoC
- How to (Advanced)