[AVR] Add AVR platform support

Author: shepmaster

config.toml.example

@@ -64,7 +64,7 @@
 # not built by default and the experimental Rust compilation targets that depend
 # on them will not work unless the user opts in to building them. By default the
 # `WebAssembly` and `RISCV` targets are enabled when compiling LLVM from scratch.
-#experimental-targets = "WebAssembly;RISCV"
+#experimental-targets = "AVR;WebAssembly;RISCV"
 
 # Cap the number of parallel linker invocations when compiling LLVM.
 # This can be useful when building LLVM with debug info, which significantly

src/bootstrap/config.rs

@@ -525,7 +525,7 @@ impl Config {
             set(&mut config.llvm_link_shared, llvm.link_shared);
             config.llvm_targets = llvm.targets.clone();
             config.llvm_experimental_targets = llvm.experimental_targets.clone()
-                .unwrap_or_else(|| "WebAssembly;RISCV".to_string());
+                .unwrap_or_else(|| "AVR;WebAssembly;RISCV".to_string());
             config.llvm_link_jobs = llvm.link_jobs;
             config.llvm_version_suffix = llvm.version_suffix.clone();
             config.llvm_clang_cl = llvm.clang_cl.clone();

src/librustc/ich/impls_syntax.rs

@@ -106,6 +106,8 @@ impl_stable_hash_for!(enum ::rustc_target::spec::abi::Abi {
     Msp430Interrupt,
     X86Interrupt,
     AmdGpuKernel,
+    AvrInterrupt,
+    AvrNonBlockingInterrupt,
     Rust,
     C,
     System,

src/librustc/ty/layout.rs

@@ -2389,6 +2389,8 @@ where
             Msp430Interrupt => Conv::Msp430Intr,
             X86Interrupt => Conv::X86Intr,
             AmdGpuKernel => Conv::AmdGpuKernel,
+            AvrInterrupt => Conv::AvrInterrupt,
+            AvrNonBlockingInterrupt => Conv::AvrNonBlockingInterrupt,
 
             // These API constants ought to be more specific...
             Cdecl => Conv::C,

src/librustc_codegen_llvm/abi.rs

@@ -371,6 +371,8 @@ impl<'tcx> FnTypeLlvmExt<'tcx> for FnType<'tcx, Ty<'tcx>> {
         match self.conv {
             Conv::C => llvm::CCallConv,
             Conv::AmdGpuKernel => llvm::AmdGpuKernel,
+            Conv::AvrInterrupt => llvm::AvrInterrupt,
+            Conv::AvrNonBlockingInterrupt => llvm::AvrNonBlockingInterrupt,
             Conv::ArmAapcs => llvm::ArmAapcsCallConv,
             Conv::Msp430Intr => llvm::Msp430Intr,
             Conv::PtxKernel => llvm::PtxKernel,

src/librustc_codegen_llvm/llvm/ffi.rs

@@ -43,6 +43,8 @@ pub enum CallConv {
     X86_64_Win64 = 79,
     X86_VectorCall = 80,
     X86_Intr = 83,
+    AvrNonBlockingInterrupt = 84,
+    AvrInterrupt = 85,
     AmdGpuKernel = 91,
 }
 

src/librustc_llvm/build.rs

@@ -70,7 +70,7 @@ fn main() {
     let is_crossed = target != host;
 
     let mut optional_components =
-        vec!["x86", "arm", "aarch64", "amdgpu", "mips", "powerpc",
+        vec!["x86", "arm", "aarch64", "amdgpu", "avr", "mips", "powerpc",
              "systemz", "jsbackend", "webassembly", "msp430", "sparc", "nvptx"];
 
     let mut version_cmd = Command::new(&llvm_config);

src/librustc_llvm/lib.rs

@@ -41,6 +41,12 @@ pub fn initialize_available_targets() {
                  LLVMInitializeARMTargetMC,
                  LLVMInitializeARMAsmPrinter,
                  LLVMInitializeARMAsmParser);
+    init_target!(llvm_component = "avr",
+                 LLVMInitializeAVRTargetInfo,
+                 LLVMInitializeAVRTarget,
+                 LLVMInitializeAVRTargetMC,
+                 LLVMInitializeAVRAsmPrinter,
+                 LLVMInitializeAVRAsmParser);
     init_target!(llvm_component = "aarch64",
                  LLVMInitializeAArch64TargetInfo,
                  LLVMInitializeAArch64Target,

src/librustc_target/abi/call/avr.rs

@@ -0,0 +1,43 @@
+// Copyright 2012-2013 The Rust Project Developers. See the COPYRIGHT
+// file at the top-level directory of this distribution and at
+// http://rust-lang.org/COPYRIGHT.
+//
+// Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
+// http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
+// <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
+// option. This file may not be copied, modified, or distributed
+// except according to those terms.
+
+#![allow(non_upper_case_globals)]
+
+use crate::abi::call::{FnType, ArgType};
+
+fn classify_ret_ty<Ty>(ret: &mut ArgType<'_, Ty>) {
+    if ret.layout.is_aggregate()  {
+        ret.make_indirect();
+    } else {
+        ret.extend_integer_width_to(8); // Is 8 correct?
+    }
+}
+
+fn classify_arg_ty<Ty>(arg: &mut ArgType<'_, Ty>) {
+    if arg.layout.is_aggregate() {
+        arg.make_indirect();
+    } else {
+        arg.extend_integer_width_to(8);
+    }
+}
+
+pub fn compute_abi_info<Ty>(fty: &mut FnType<'_, Ty>) {
+    if !fty.ret.is_ignore() {
+        classify_ret_ty(&mut fty.ret);
+    }
+
+    for arg in &mut fty.args {
+        if arg.is_ignore() {
+            continue;
+        }
+
+        classify_arg_ty(arg);
+    }
+}

src/librustc_target/abi/call/mod.rs

@@ -6,6 +6,7 @@ mod aarch64;
 mod amdgpu;
 mod arm;
 mod asmjs;
+mod avr;
 mod hexagon;
 mod mips;
 mod mips64;
@@ -516,6 +517,8 @@ pub enum Conv {
     X86_64Win64,
 
     AmdGpuKernel,
+    AvrInterrupt,
+    AvrNonBlockingInterrupt,
 }
 
 /// Metadata describing how the arguments to a native function
@@ -573,6 +576,7 @@ impl<'a, Ty> FnType<'a, Ty> {
                     wasm32::compute_abi_info(self)
                 }
             }
+            "avr" => avr::compute_abi_info(self),
             "msp430" => msp430::compute_abi_info(self),
             "sparc" => sparc::compute_abi_info(cx, self),
             "sparc64" => sparc64::compute_abi_info(cx, self),