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static inline void gpio_mode_set_input (uint32_t pin , uint32_t pull_up_down )
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{
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- gpio_mode_set (input_port , GPIO_MODE_INPUT , pull_up_down , pin );
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+ gpio_mode_set (input_port , GPIO_MODE_INPUT , pull_up_down , pin );
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}
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static inline void gpio_mode_set_output (uint32_t pin , uint32_t output_mode )
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{
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- gpio_mode_set (input_port , GPIO_MODE_OUTPUT , output_mode , pin );
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+ gpio_mode_set (input_port , GPIO_MODE_OUTPUT , output_mode , pin );
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}
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static inline void gpio_set (uint32_t pin )
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{
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- gpio_bit_set (input_port , pin );
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+ gpio_bit_set (input_port , pin );
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}
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static inline void gpio_clear (uint32_t pin )
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{
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- gpio_bit_reset (input_port , pin );
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+ gpio_bit_reset (input_port , pin );
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}
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static inline bool gpio_read (uint32_t pin )
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{
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- return (gpio_input_port_get (input_port ) & pin ) != 0 ;
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+ return (gpio_input_port_get (input_port ) & pin ) != 0 ;
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}
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#define BL_TIMER TIMER16
@@ -55,33 +55,33 @@ static inline bool gpio_read(uint32_t pin)
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*/
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static inline void bl_timer_init (void )
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{
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- rcu_periph_clock_enable (RCU_TIMER16 );
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- TIMER_CAR (BL_TIMER ) = 0xFFFF ;
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- TIMER_PSC (BL_TIMER ) = 71 ;
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- timer_auto_reload_shadow_enable (BL_TIMER );
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- timer_enable (BL_TIMER );
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+ rcu_periph_clock_enable (RCU_TIMER16 );
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+ TIMER_CAR (BL_TIMER ) = 0xFFFF ;
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+ TIMER_PSC (BL_TIMER ) = 71 ;
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+ timer_auto_reload_shadow_enable (BL_TIMER );
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+ timer_enable (BL_TIMER );
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}
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/*
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disable timer ready for app start
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*/
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static inline void bl_timer_disable (void )
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{
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- timer_disable (BL_TIMER );
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+ timer_disable (BL_TIMER );
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}
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static inline uint16_t bl_timer_us (void )
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{
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- return timer_counter_read (BL_TIMER );
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+ return timer_counter_read (BL_TIMER );
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}
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/*
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initialise clocks
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*/
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static inline void bl_clock_config (void )
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{
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- rcu_periph_clock_enable (RCU_GPIOA );
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- rcu_periph_clock_enable (RCU_GPIOB );
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+ rcu_periph_clock_enable (RCU_GPIOA );
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+ rcu_periph_clock_enable (RCU_GPIOB );
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}
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static inline void bl_gpio_init (void )
@@ -93,30 +93,30 @@ static inline void bl_gpio_init(void)
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*/
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static inline bool bl_was_software_reset (void )
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{
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- return (RCU_RSTSCK & RCU_RSTSCK_SWRSTF ) != 0 ;
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+ return (RCU_RSTSCK & RCU_RSTSCK_SWRSTF ) != 0 ;
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}
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/*
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jump from the bootloader to the application code
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*/
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static inline void jump_to_application (void )
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{
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- __disable_irq ();
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- bl_timer_disable ();
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- const uint32_t app_address = MCU_FLASH_START + FIRMWARE_RELATIVE_START ;
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- const uint32_t * app_data = (const uint32_t * )app_address ;
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- const uint32_t stack_top = app_data [0 ];
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- const uint32_t JumpAddress = app_data [1 ];
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+ __disable_irq ();
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+ bl_timer_disable ();
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+ const uint32_t app_address = MCU_FLASH_START + FIRMWARE_RELATIVE_START ;
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+ const uint32_t * app_data = (const uint32_t * )app_address ;
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+ const uint32_t stack_top = app_data [0 ];
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+ const uint32_t JumpAddress = app_data [1 ];
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- // setup vector table
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- SCB -> VTOR = app_address ;
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+ // setup vector table
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+ SCB -> VTOR = app_address ;
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- // setup sp, msp and jump
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- asm volatile (
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- "mov sp, %0 \n"
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- "msr msp, %0 \n"
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- "bx %1 \n"
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- : : "r" (stack_top ), "r" (JumpAddress ) :);
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+ // setup sp, msp and jump
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+ asm volatile (
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+ "mov sp, %0 \n"
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+ "msr msp, %0 \n"
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+ "bx %1 \n"
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+ : : "r" (stack_top ), "r" (JumpAddress ) :);
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}
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void SysTick_Handler (void )
@@ -138,51 +138,51 @@ void SysTick_Handler(void)
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static void system_clock_72m_irc8m (void )
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{
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- uint32_t timeout = 0U ;
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- uint32_t stab_flag = 0U ;
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+ uint32_t timeout = 0U ;
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+ uint32_t stab_flag = 0U ;
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- /* enable IRC8M */
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- RCU_CTL0 |= RCU_CTL0_IRC8MEN ;
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+ /* enable IRC8M */
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+ RCU_CTL0 |= RCU_CTL0_IRC8MEN ;
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- /* wait until IRC8M is stable or the startup time is longer than
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- * IRC8M_STARTUP_TIMEOUT */
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- do {
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- timeout ++ ;
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- stab_flag = (RCU_CTL0 & RCU_CTL0_IRC8MSTB );
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- } while ((0U == stab_flag ) && (IRC8M_STARTUP_TIMEOUT != timeout ));
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+ /* wait until IRC8M is stable or the startup time is longer than
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+ * IRC8M_STARTUP_TIMEOUT */
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+ do {
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+ timeout ++ ;
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+ stab_flag = (RCU_CTL0 & RCU_CTL0_IRC8MSTB );
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+ } while ((0U == stab_flag ) && (IRC8M_STARTUP_TIMEOUT != timeout ));
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- /* if fail */
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- if (0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB )) {
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- while (1 ) {
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- }
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+ /* if fail */
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+ if (0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB )) {
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+ while (1 ) {
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}
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+ }
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- FMC_WS = (FMC_WS & (~FMC_WS_WSCNT )) | WS_WSCNT_2 ;
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+ FMC_WS = (FMC_WS & (~FMC_WS_WSCNT )) | WS_WSCNT_2 ;
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- /* AHB = SYSCLK */
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- RCU_CFG0 |= RCU_AHB_CKSYS_DIV1 ;
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- /* APB2 = AHB */
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- RCU_CFG0 |= RCU_APB2_CKAHB_DIV1 ;
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- /* APB1 = AHB */
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- RCU_CFG0 |= RCU_APB1_CKAHB_DIV1 ;
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- /* PLL = (IRC8M/2) * 18 = 72 MHz */
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- RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF );
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- RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18 );
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+ /* AHB = SYSCLK */
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+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1 ;
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+ /* APB2 = AHB */
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+ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1 ;
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+ /* APB1 = AHB */
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+ RCU_CFG0 |= RCU_APB1_CKAHB_DIV1 ;
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+ /* PLL = (IRC8M/2) * 18 = 72 MHz */
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+ RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF );
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+ RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18 );
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- /* enable PLL */
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- RCU_CTL0 |= RCU_CTL0_PLLEN ;
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+ /* enable PLL */
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+ RCU_CTL0 |= RCU_CTL0_PLLEN ;
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- /* wait until PLL is stable */
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- while (0U == (RCU_CTL0 & RCU_CTL0_PLLSTB )) {
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- }
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+ /* wait until PLL is stable */
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+ while (0U == (RCU_CTL0 & RCU_CTL0_PLLSTB )) {
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+ }
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- /* select PLL as system clock */
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- RCU_CFG0 &= ~RCU_CFG0_SCS ;
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- RCU_CFG0 |= RCU_CKSYSSRC_PLL ;
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+ /* select PLL as system clock */
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+ RCU_CFG0 &= ~RCU_CFG0_SCS ;
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+ RCU_CFG0 |= RCU_CKSYSSRC_PLL ;
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- /* wait until PLL is selected as system clock */
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- while (0U == (RCU_CFG0 & RCU_SCSS_PLL )) {
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- }
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+ /* wait until PLL is selected as system clock */
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+ while (0U == (RCU_CFG0 & RCU_SCSS_PLL )) {
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+ }
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}
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/*!
@@ -193,7 +193,7 @@ static void system_clock_72m_irc8m(void)
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*/
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static void system_clock_config (void )
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{
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- system_clock_72m_irc8m ();
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+ system_clock_72m_irc8m ();
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}
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/*!
@@ -204,24 +204,24 @@ static void system_clock_config(void)
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*/
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void SystemInit (void )
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{
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- /* enable IRC8M */
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- RCU_CTL0 |= RCU_CTL0_IRC8MEN ;
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- while (0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB )) {
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- }
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-
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- RCU_MODIFY (0x80 );
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- RCU_CFG0 &= ~RCU_CFG0_SCS ;
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- RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS );
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- /* reset RCU */
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- RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV );
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- RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV );
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- RCU_CFG1 &= ~(RCU_CFG1_PREDV );
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- RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL );
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- RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV ;
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- RCU_CFG2 &= ~RCU_CFG2_ADCPSC2 ;
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- RCU_CTL1 &= ~RCU_CTL1_IRC28MEN ;
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- RCU_INT = 0x00000000U ;
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-
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- /* configure system clock */
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- system_clock_config ();
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+ /* enable IRC8M */
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+ RCU_CTL0 |= RCU_CTL0_IRC8MEN ;
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+ while (0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB )) {
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+ }
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+
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+ RCU_MODIFY (0x80 );
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+ RCU_CFG0 &= ~RCU_CFG0_SCS ;
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+ RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS );
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+ /* reset RCU */
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+ RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV );
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+ RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV );
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+ RCU_CFG1 &= ~(RCU_CFG1_PREDV );
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+ RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL );
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+ RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV ;
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+ RCU_CFG2 &= ~RCU_CFG2_ADCPSC2 ;
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+ RCU_CTL1 &= ~RCU_CTL1_IRC28MEN ;
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+ RCU_INT = 0x00000000U ;
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+
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+ /* configure system clock */
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+ system_clock_config ();
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}
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