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Commit 29cc6a9

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global reformatting to match AM32 code style
1 parent a414b20 commit 29cc6a9

34 files changed

+2716
-2799
lines changed

Mcu/e230/Inc/blutil.h

Lines changed: 85 additions & 85 deletions
Original file line numberDiff line numberDiff line change
@@ -25,27 +25,27 @@
2525

2626
static inline void gpio_mode_set_input(uint32_t pin, uint32_t pull_up_down)
2727
{
28-
gpio_mode_set(input_port, GPIO_MODE_INPUT, pull_up_down, pin);
28+
gpio_mode_set(input_port, GPIO_MODE_INPUT, pull_up_down, pin);
2929
}
3030

3131
static inline void gpio_mode_set_output(uint32_t pin, uint32_t output_mode)
3232
{
33-
gpio_mode_set(input_port, GPIO_MODE_OUTPUT, output_mode, pin);
33+
gpio_mode_set(input_port, GPIO_MODE_OUTPUT, output_mode, pin);
3434
}
3535

3636
static inline void gpio_set(uint32_t pin)
3737
{
38-
gpio_bit_set(input_port, pin);
38+
gpio_bit_set(input_port, pin);
3939
}
4040

4141
static inline void gpio_clear(uint32_t pin)
4242
{
43-
gpio_bit_reset(input_port, pin);
43+
gpio_bit_reset(input_port, pin);
4444
}
4545

4646
static inline bool gpio_read(uint32_t pin)
4747
{
48-
return (gpio_input_port_get(input_port) & pin) != 0;
48+
return (gpio_input_port_get(input_port) & pin) != 0;
4949
}
5050

5151
#define BL_TIMER TIMER16
@@ -55,33 +55,33 @@ static inline bool gpio_read(uint32_t pin)
5555
*/
5656
static inline void bl_timer_init(void)
5757
{
58-
rcu_periph_clock_enable(RCU_TIMER16);
59-
TIMER_CAR(BL_TIMER) = 0xFFFF;
60-
TIMER_PSC(BL_TIMER) = 71;
61-
timer_auto_reload_shadow_enable(BL_TIMER);
62-
timer_enable(BL_TIMER);
58+
rcu_periph_clock_enable(RCU_TIMER16);
59+
TIMER_CAR(BL_TIMER) = 0xFFFF;
60+
TIMER_PSC(BL_TIMER) = 71;
61+
timer_auto_reload_shadow_enable(BL_TIMER);
62+
timer_enable(BL_TIMER);
6363
}
6464

6565
/*
6666
disable timer ready for app start
6767
*/
6868
static inline void bl_timer_disable(void)
6969
{
70-
timer_disable(BL_TIMER);
70+
timer_disable(BL_TIMER);
7171
}
7272

7373
static inline uint16_t bl_timer_us(void)
7474
{
75-
return timer_counter_read(BL_TIMER);
75+
return timer_counter_read(BL_TIMER);
7676
}
7777

7878
/*
7979
initialise clocks
8080
*/
8181
static inline void bl_clock_config(void)
8282
{
83-
rcu_periph_clock_enable(RCU_GPIOA);
84-
rcu_periph_clock_enable(RCU_GPIOB);
83+
rcu_periph_clock_enable(RCU_GPIOA);
84+
rcu_periph_clock_enable(RCU_GPIOB);
8585
}
8686

8787
static inline void bl_gpio_init(void)
@@ -93,30 +93,30 @@ static inline void bl_gpio_init(void)
9393
*/
9494
static inline bool bl_was_software_reset(void)
9595
{
96-
return (RCU_RSTSCK & RCU_RSTSCK_SWRSTF) != 0;
96+
return (RCU_RSTSCK & RCU_RSTSCK_SWRSTF) != 0;
9797
}
9898

9999
/*
100100
jump from the bootloader to the application code
101101
*/
102102
static inline void jump_to_application(void)
103103
{
104-
__disable_irq();
105-
bl_timer_disable();
106-
const uint32_t app_address = MCU_FLASH_START + FIRMWARE_RELATIVE_START;
107-
const uint32_t *app_data = (const uint32_t *)app_address;
108-
const uint32_t stack_top = app_data[0];
109-
const uint32_t JumpAddress = app_data[1];
104+
__disable_irq();
105+
bl_timer_disable();
106+
const uint32_t app_address = MCU_FLASH_START + FIRMWARE_RELATIVE_START;
107+
const uint32_t *app_data = (const uint32_t *)app_address;
108+
const uint32_t stack_top = app_data[0];
109+
const uint32_t JumpAddress = app_data[1];
110110

111-
// setup vector table
112-
SCB->VTOR = app_address;
111+
// setup vector table
112+
SCB->VTOR = app_address;
113113

114-
// setup sp, msp and jump
115-
asm volatile(
116-
"mov sp, %0 \n"
117-
"msr msp, %0 \n"
118-
"bx %1 \n"
119-
: : "r"(stack_top), "r"(JumpAddress) :);
114+
// setup sp, msp and jump
115+
asm volatile(
116+
"mov sp, %0 \n"
117+
"msr msp, %0 \n"
118+
"bx %1 \n"
119+
: : "r"(stack_top), "r"(JumpAddress) :);
120120
}
121121

122122
void SysTick_Handler(void)
@@ -138,51 +138,51 @@ void SysTick_Handler(void)
138138

139139
static void system_clock_72m_irc8m(void)
140140
{
141-
uint32_t timeout = 0U;
142-
uint32_t stab_flag = 0U;
141+
uint32_t timeout = 0U;
142+
uint32_t stab_flag = 0U;
143143

144-
/* enable IRC8M */
145-
RCU_CTL0 |= RCU_CTL0_IRC8MEN;
144+
/* enable IRC8M */
145+
RCU_CTL0 |= RCU_CTL0_IRC8MEN;
146146

147-
/* wait until IRC8M is stable or the startup time is longer than
148-
* IRC8M_STARTUP_TIMEOUT */
149-
do {
150-
timeout++;
151-
stab_flag = (RCU_CTL0 & RCU_CTL0_IRC8MSTB);
152-
} while ((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
147+
/* wait until IRC8M is stable or the startup time is longer than
148+
* IRC8M_STARTUP_TIMEOUT */
149+
do {
150+
timeout++;
151+
stab_flag = (RCU_CTL0 & RCU_CTL0_IRC8MSTB);
152+
} while ((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
153153

154-
/* if fail */
155-
if (0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)) {
156-
while (1) {
157-
}
154+
/* if fail */
155+
if (0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)) {
156+
while (1) {
158157
}
158+
}
159159

160-
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT_2;
160+
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT_2;
161161

162-
/* AHB = SYSCLK */
163-
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
164-
/* APB2 = AHB */
165-
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
166-
/* APB1 = AHB */
167-
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
168-
/* PLL = (IRC8M/2) * 18 = 72 MHz */
169-
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
170-
RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18);
162+
/* AHB = SYSCLK */
163+
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
164+
/* APB2 = AHB */
165+
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
166+
/* APB1 = AHB */
167+
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
168+
/* PLL = (IRC8M/2) * 18 = 72 MHz */
169+
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
170+
RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18);
171171

172-
/* enable PLL */
173-
RCU_CTL0 |= RCU_CTL0_PLLEN;
172+
/* enable PLL */
173+
RCU_CTL0 |= RCU_CTL0_PLLEN;
174174

175-
/* wait until PLL is stable */
176-
while (0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)) {
177-
}
175+
/* wait until PLL is stable */
176+
while (0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)) {
177+
}
178178

179-
/* select PLL as system clock */
180-
RCU_CFG0 &= ~RCU_CFG0_SCS;
181-
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
179+
/* select PLL as system clock */
180+
RCU_CFG0 &= ~RCU_CFG0_SCS;
181+
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
182182

183-
/* wait until PLL is selected as system clock */
184-
while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) {
185-
}
183+
/* wait until PLL is selected as system clock */
184+
while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) {
185+
}
186186
}
187187

188188
/*!
@@ -193,7 +193,7 @@ static void system_clock_72m_irc8m(void)
193193
*/
194194
static void system_clock_config(void)
195195
{
196-
system_clock_72m_irc8m();
196+
system_clock_72m_irc8m();
197197
}
198198

199199
/*!
@@ -204,24 +204,24 @@ static void system_clock_config(void)
204204
*/
205205
void SystemInit(void)
206206
{
207-
/* enable IRC8M */
208-
RCU_CTL0 |= RCU_CTL0_IRC8MEN;
209-
while (0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)) {
210-
}
211-
212-
RCU_MODIFY(0x80);
213-
RCU_CFG0 &= ~RCU_CFG0_SCS;
214-
RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
215-
/* reset RCU */
216-
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
217-
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
218-
RCU_CFG1 &= ~(RCU_CFG1_PREDV);
219-
RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL);
220-
RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
221-
RCU_CFG2 &= ~RCU_CFG2_ADCPSC2;
222-
RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
223-
RCU_INT = 0x00000000U;
224-
225-
/* configure system clock */
226-
system_clock_config();
207+
/* enable IRC8M */
208+
RCU_CTL0 |= RCU_CTL0_IRC8MEN;
209+
while (0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)) {
210+
}
211+
212+
RCU_MODIFY(0x80);
213+
RCU_CFG0 &= ~RCU_CFG0_SCS;
214+
RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
215+
/* reset RCU */
216+
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
217+
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
218+
RCU_CFG1 &= ~(RCU_CFG1_PREDV);
219+
RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL);
220+
RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
221+
RCU_CFG2 &= ~RCU_CFG2_ADCPSC2;
222+
RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
223+
RCU_INT = 0x00000000U;
224+
225+
/* configure system clock */
226+
system_clock_config();
227227
}

Mcu/e230/Src/eeprom.c

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -8,35 +8,35 @@
88

99
bool save_flash_nolib(const uint8_t* data, uint32_t length, uint32_t add)
1010
{
11-
if ((add & 0x3) != 0 || (length & 0x3) != 0) {
12-
return false;
13-
}
14-
const uint32_t data_length = length / 4;
15-
16-
// unlock flash
17-
18-
fmc_unlock();
19-
20-
// erase page if address even divisable by 1024
21-
if ((add % page_size) == 0) {
22-
fmc_page_erase(add);
23-
}
24-
25-
volatile uint32_t index = 0;
26-
while (index < data_length) {
27-
uint32_t word;
28-
memcpy(&word, (void*)(data+(index*4)), sizeof(word));
29-
fmc_word_program(add + (index * 4), word);
30-
fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_WPERR | FMC_FLAG_PGERR);
31-
index++;
32-
}
33-
fmc_lock();
34-
35-
// ensure data is correct
36-
return memcmp(data, (const void *)add, length) == 0;
11+
if ((add & 0x3) != 0 || (length & 0x3) != 0) {
12+
return false;
13+
}
14+
const uint32_t data_length = length / 4;
15+
16+
// unlock flash
17+
18+
fmc_unlock();
19+
20+
// erase page if address even divisable by 1024
21+
if ((add % page_size) == 0) {
22+
fmc_page_erase(add);
23+
}
24+
25+
volatile uint32_t index = 0;
26+
while (index < data_length) {
27+
uint32_t word;
28+
memcpy(&word, (void*)(data+(index*4)), sizeof(word));
29+
fmc_word_program(add + (index * 4), word);
30+
fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_WPERR | FMC_FLAG_PGERR);
31+
index++;
32+
}
33+
fmc_lock();
34+
35+
// ensure data is correct
36+
return memcmp(data, (const void *)add, length) == 0;
3737
}
3838

3939
void read_flash_bin(uint8_t* data, uint32_t add, int out_buff_len)
4040
{
41-
memcpy(data, (void*)add, out_buff_len);
41+
memcpy(data, (void*)add, out_buff_len);
4242
}

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