Is there a specific SystemRDL syntax to specify that an array of registers would be implemented as RAM (when generating SystemVerilog with PeakRDL)

[martin-tanguay]

Hi,

Is there a specific SystemRDL syntax to specify that an array of registers would be implemented as RAM (when generating SystemVerilog with PeakRDL) ?

Thanks.

Martin Tanguay

[amykyta3]

No not currently. The PeakRDL-regblock exporter generally stays within the bounds of what can be normally described with the built-in SystemRDL properties.
In this case I would recommend using an external mem instance, which would break out an external interface that would allow you to connect it to a RAM. See this page for more details: https://peakrdl-regblock.readthedocs.io/en/latest/rdl_features/external.html