diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c
index 4f674d0aef9..2adb1a9b99f 100644
--- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c
+++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c
@@ -61,14 +61,13 @@
 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
 {
     GPIO_InitTypeDef GPIO_InitStruct;
-    if(heth->Instance == ETH)
-    {
+    if (heth->Instance == ETH) {
         enableEthPowerSupply();
-        
-        #if !(defined(DUAL_CORE) && defined(CORE_CM4))
+
+#if !(defined(DUAL_CORE) && defined(CORE_CM4))
         /* Disable DCache for STM32H7 family */
         SCB_DisableDCache();
-        #endif
+#endif
 
         /* GPIO Ports Clock Enable */
         __HAL_RCC_GPIOA_CLK_ENABLE();
@@ -118,21 +117,21 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
         PC4     ------> ETH_RXD0
         PC5     ------> ETH_RXD1
         */
-        GPIO_InitStruct.Pin = ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin;
+        GPIO_InitStruct.Pin = ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin;
         GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
         GPIO_InitStruct.Pull = GPIO_NOPULL;
         GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
         GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
         HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
 
-        GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin;
+        GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin;
         GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
         GPIO_InitStruct.Pull = GPIO_NOPULL;
         GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
         GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
         HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 
-        GPIO_InitStruct.Pin = ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin;
+        GPIO_InitStruct.Pin = ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin;
         GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
         GPIO_InitStruct.Pull = GPIO_NOPULL;
         GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
@@ -146,8 +145,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
  */
 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
 {
-    if(heth->Instance == ETH)
-    {
+    if (heth->Instance == ETH) {
         /* Peripheral clock disable */
         __HAL_RCC_ETH1MAC_CLK_DISABLE();
         __HAL_RCC_ETH1TX_CLK_DISABLE();
@@ -164,11 +162,11 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
         PC4     ------> ETH_RXD0
         PC5     ------> ETH_RXD1
         */
-        HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin);
+        HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin);
 
-        HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin);
+        HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin);
 
-        HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin);
+        HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin);
 
         HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 0);
     }
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F070xB/system_clock.c b/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F070xB/system_clock.c
index 1d4fe38c841..91c76da81b8 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F070xB/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F070xB/system_clock.c
@@ -95,7 +95,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     //Select HSI as system clock source to allow modification of the PLL configuration
     RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
     RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
-    if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
         return 0; // FAIL
     }
 
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F072xB/system_clock.c b/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F072xB/system_clock.c
index 8317759ebf2..a5aa3bd1eac 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F072xB/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F072xB/system_clock.c
@@ -95,7 +95,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     //Select HSI as system clock source to allow modification of the PLL configuration
     RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
     RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
-    if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
         return 0; // FAIL
     }
 
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F091xC/system_clock.c b/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F091xC/system_clock.c
index d354280b678..b3155300d4b 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F091xC/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F091xC/system_clock.c
@@ -95,7 +95,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     //Select HSI as system clock source to allow modification of the PLL configuration
     RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
     RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
-    if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
         return 0; // FAIL
     }
 
diff --git a/targets/TARGET_STM/TARGET_STM32F0/cmsis_nvic.c b/targets/TARGET_STM/TARGET_STM32F0/cmsis_nvic.c
index 0124d0edaa9..3ce3bd3c654 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/cmsis_nvic.c
+++ b/targets/TARGET_STM/TARGET_STM32F0/cmsis_nvic.c
@@ -18,24 +18,26 @@
 
 #define NVIC_USER_IRQ_OFFSET  16
 
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
     int i;
 
     // Copy and switch to dynamic vectors if first time called
     if ((SYSCFG->CFGR1 & SYSCFG_CFGR1_MEM_MODE) != SYSCFG_CFGR1_MEM_MODE) {
         uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
         for (i = 0; i < NVIC_NUM_VECTORS; i++) {
-            *((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (i*4))) = old_vectors[i];
+            *((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (i * 4))) = old_vectors[i];
         }
         SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE; // Embedded SRAM mapped at 0x00000000
     }
 
     // Set the vector
-    *((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (IRQn*4) + (NVIC_USER_IRQ_OFFSET*4))) = vector;
+    *((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (IRQn * 4) + (NVIC_USER_IRQ_OFFSET * 4))) = vector;
 }
 
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
     // Return the vector
     return vectors[IRQn + 16];
 }
diff --git a/targets/TARGET_STM/TARGET_STM32F0/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32F0/us_ticker_data.h
index 10d646cbb25..d79efc3d0eb 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/us_ticker_data.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/us_ticker_data.h
@@ -17,7 +17,7 @@
 #define __US_TICKER_DATA_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 #include "stm32f0xx.h"
diff --git a/targets/TARGET_STM/TARGET_STM32F3/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32F3/us_ticker_data.h
index 043950aee96..713e11a11d9 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/us_ticker_data.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/us_ticker_data.h
@@ -18,13 +18,13 @@
 #define __US_TICKER_DATA_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 #include "stm32f3xx.h"
 #include "stm32f3xx_ll_tim.h"
 #include "cmsis_nvic.h"
-   
+
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/system_clock.c
index e7f27727b88..e60fee8f1d4 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/system_clock.c
@@ -106,8 +106,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
 
     /* PLL could be already configured by bootlader */
-    if (RCC_OscInitStruct.PLL.PLLState != RCC_PLL_ON)
-    {
+    if (RCC_OscInitStruct.PLL.PLLState != RCC_PLL_ON) {
         /* Enable HSE oscillator and activate PLL with HSE as source */
         RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
         if (bypass == 0) {
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/TargetInit.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/TargetInit.c
index 38905fb0a71..c9c89ca9858 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/TargetInit.c
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/TargetInit.c
@@ -15,7 +15,8 @@
 
 #include "stm32f4xx.h"
 
-void TargetBSP_Init(void) {
+void TargetBSP_Init(void)
+{
     /* In DISCO_F413ZH board, Arduino connector and Wifi embeded module are sharing the same SPI pins */
     /* We need to set the default SPI SS pin for the Wifi module to the inactive state i.e. 1 */
     /* See board User Manual: WIFI_SPI_CS = PG_11*/
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h
index 0a023971f37..1770f451d5c 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h
@@ -290,7 +290,7 @@ typedef enum {
     D69 = PF_1,
     D70 = PF_2,
     D71 = PA_7,
-    
+
     // STDIO for console print
 #ifdef MBED_CONF_TARGET_STDIO_UART_TX
     CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX,
@@ -394,4 +394,3 @@ typedef enum {
 #endif
 
 #endif
-    
\ No newline at end of file
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h
index 127813a35f8..b4b02a07cbc 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h
@@ -287,7 +287,7 @@ typedef enum {
     D69 = PF_1,
     D70 = PF_2,
     D71 = PA_7,
-    
+
     // STDIO for console print
 #ifdef MBED_CONF_TARGET_STDIO_UART_TX
     CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX,
@@ -387,4 +387,3 @@ typedef enum {
 #endif
 
 #endif
-    
\ No newline at end of file
diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/cmsis_nvic.h
index 86a986e6f9d..8045b5a794f 100644
--- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/cmsis_nvic.h
+++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/cmsis_nvic.h
@@ -23,8 +23,8 @@
 
 #if !defined(MBED_ROM_SIZE)
 #define MBED_ROM_SIZE  0x10000
- //  0x10000 STM32G030K8Tx STM32G030C8Tx 
- //   0x8000 STM32G030F6Px STM32G030K6Tx STM32G030C6Tx STM32G030J6Mx 
+//  0x10000 STM32G030K8Tx STM32G030C8Tx
+//   0x8000 STM32G030F6Px STM32G030K6Tx STM32G030C6Tx STM32G030J6Mx
 #endif
 
 #if !defined(MBED_RAM_START)
diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/cmsis_nvic.h
index 2c6795b12d2..4c135e696f5 100644
--- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/cmsis_nvic.h
+++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/cmsis_nvic.h
@@ -23,8 +23,8 @@
 
 #if !defined(MBED_ROM_SIZE)
 #define MBED_ROM_SIZE  0x10000
- //  0x10000 STM32G041Y8Yx STM32G041K8Ux STM32G041C8Ux STM32G041C8Tx STM32G041K8Tx STM32G041G8Ux STM32G041F8Px 
- //   0x8000 STM32G041G6Ux STM32G041K6Tx STM32G041C6Tx STM32G041J6Mx STM32G041K6Ux STM32G041C6Ux STM32G041F6Px 
+//  0x10000 STM32G041Y8Yx STM32G041K8Ux STM32G041C8Ux STM32G041C8Tx STM32G041K8Tx STM32G041G8Ux STM32G041F8Px
+//   0x8000 STM32G041G6Ux STM32G041K6Tx STM32G041C6Tx STM32G041J6Mx STM32G041K6Ux STM32G041C6Ux STM32G041F6Px
 #endif
 
 #if !defined(MBED_RAM_START)
diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/cmsis_nvic.h
index 02e1da1b2ec..49b2a4318ac 100644
--- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/cmsis_nvic.h
+++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/cmsis_nvic.h
@@ -25,9 +25,9 @@
 #if defined (TARGET_NUCLEO_G071RB)
 #define MBED_ROM_SIZE  0x20000
 #else
- //  0x10000 STM32G071C8Ux STM32G071K8TxN STM32G071R8Tx STM32G071K8Ux STM32G071G8UxN STM32G071C8Tx STM32G071K8Tx STM32G071K8UxN STM32G071G8Ux 
- //   0x8000 STM32G071K6Tx STM32G071G6Ux STM32G071C6Tx STM32G071K6Ux STM32G071R6Tx STM32G071C6Ux 
- //  0x20000 STM32G071GBUxN STM32G071CBUx STM32G071KBTx STM32G071KBUxN STM32G071RBTx STM32G071EBYx STM32G071GBUx STM32G071CBTx STM32G071KBUx STM32G071RBIx STM32G071KBTxN 
+//  0x10000 STM32G071C8Ux STM32G071K8TxN STM32G071R8Tx STM32G071K8Ux STM32G071G8UxN STM32G071C8Tx STM32G071K8Tx STM32G071K8UxN STM32G071G8Ux
+//   0x8000 STM32G071K6Tx STM32G071G6Ux STM32G071C6Tx STM32G071K6Ux STM32G071R6Tx STM32G071C6Ux
+//  0x20000 STM32G071GBUxN STM32G071CBUx STM32G071KBTx STM32G071KBUxN STM32G071RBTx STM32G071EBYx STM32G071GBUx STM32G071CBTx STM32G071KBUx STM32G071RBIx STM32G071KBTxN
 #error "MBED_ROM_SIZE not defined"
 #endif
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TARGET_NUCLEO_G474RE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TARGET_NUCLEO_G474RE/PeripheralPins.c
index f92db38c86e..2792b486f96 100644
--- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TARGET_NUCLEO_G474RE/PeripheralPins.c
+++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TARGET_NUCLEO_G474RE/PeripheralPins.c
@@ -246,15 +246,15 @@ MBED_WEAK const PinMap PinMap_PWM[] = {
 
 MBED_WEAK const PinMap PinMap_UART_TX[] = {
     {PA_2,       UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX
-    {PA_2_ALT0,  LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, // Connected to STDIO_UART_RX
+    {PA_2_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, // Connected to STDIO_UART_RX
     {PA_9,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PA_14,      UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to T_SWCLK
     {PB_3,       UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to T_SWO
     {PB_6,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_9,       UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     {PB_10,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-    {PB_11,      LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
-    {PC_1,       LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_11,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_1,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {PC_4,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PC_10,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     {PC_10_ALT0, UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)},
@@ -264,15 +264,15 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = {
 
 MBED_WEAK const PinMap PinMap_UART_RX[] = {
     {PA_3,       UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX
-    {PA_3_ALT0,  LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, // Connected to STDIO_UART_TX
+    {PA_3_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, // Connected to STDIO_UART_TX
     {PA_10,      UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PA_15,      UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {PB_4,       UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {PB_7,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_8,       UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-    {PB_10,      LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_10,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {PB_11,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-    {PC_0,       LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_0,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {PC_5,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PC_11,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     {PC_11_ALT0, UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)},
@@ -284,22 +284,22 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = {
     {PA_1,       UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {PA_12,      UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PA_15,      UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
-    {PB_1,       LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)},
+    {PB_1,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)},
     {PB_4,       UART_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
-    {PB_12,      LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_12,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {PB_14,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     {NC, NC, 0}
 };
 
 MBED_WEAK const PinMap PinMap_UART_CTS[] = {
     {PA_0,       UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
-    {PA_6,       LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)},
+    {PA_6,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)},
     {PA_11,      UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PA_13,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to T_SWDIO
     {PB_5,       UART_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)},
     {PB_7,       UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART4)},
     {PB_13,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-    {PB_13_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {NC, NC, 0}
 };
 
diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp
index 0d430bfc95d..13ba1042de5 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp
+++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp
@@ -26,27 +26,27 @@
  ******************************************************************************/
 void enableEthPowerSupply(void)
 {
-  /* Ensure ETH power supply */
-  mbed::I2C i2c(PB_7, PB_6);
-  
-  char data[2];
-
-  // LDO3 to 1.2V
-  data[0]=0x52;
-  data[1]=0x9;
-  i2c.write(8 << 1, data, sizeof(data));
-  data[0]=0x53;
-  data[1]=0xF;
-  i2c.write(8 << 1, data, sizeof(data));
-  
-  // SW2 to 3.3V (SW2_VOLT)
-  data[0]=0x3B;
-  data[1]=0xF;
-  i2c.write(8 << 1, data, sizeof(data));
-
-  // SW1 to 3.0V (SW1_VOLT)
-  data[0]=0x35;
-  data[1]=0xF;
-  i2c.write(8 << 1, data, sizeof(data));
-  
+    /* Ensure ETH power supply */
+    mbed::I2C i2c(PB_7, PB_6);
+
+    char data[2];
+
+    // LDO3 to 1.2V
+    data[0] = 0x52;
+    data[1] = 0x9;
+    i2c.write(8 << 1, data, sizeof(data));
+    data[0] = 0x53;
+    data[1] = 0xF;
+    i2c.write(8 << 1, data, sizeof(data));
+
+    // SW2 to 3.3V (SW2_VOLT)
+    data[0] = 0x3B;
+    data[1] = 0xF;
+    i2c.write(8 << 1, data, sizeof(data));
+
+    // SW1 to 3.0V (SW1_VOLT)
+    data[0] = 0x35;
+    data[1] = 0xF;
+    i2c.write(8 << 1, data, sizeof(data));
+
 }
diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c
index 3b2a5304620..ae7821ede03 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c
@@ -68,9 +68,9 @@ uint8_t SetSysClock_PLL_HSI(void);
 void SetSysClock(void)
 {
 
-  bool lowspeed = false;
+    bool lowspeed = false;
 #if defined(LOWSPEED) && (LOWSPEED == 1)
-  lowspeed = true;
+    lowspeed = true;
 #endif
 
 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
@@ -95,17 +95,19 @@ void SetSysClock(void)
 }
 
 static const uint32_t _keep;
-bool isBootloader() {
-  return ((uint32_t)&_keep < 0x8040000);
+bool isBootloader()
+{
+    return ((uint32_t)&_keep < 0x8040000);
 }
 
-bool isBetaBoard() {
-  uint8_t* bootloader_data = (uint8_t*)(0x801F000);
-  if (bootloader_data[0] != 0xA0 || bootloader_data[1] < 14) {
-    return true;
-  } else {
-    return (bootloader_data[10] == 27);
-  }
+bool isBetaBoard()
+{
+    uint8_t *bootloader_data = (uint8_t *)(0x801F000);
+    if (bootloader_data[0] != 0xA0 || bootloader_data[1] < 14) {
+        return true;
+    } else {
+        return (bootloader_data[10] == 27);
+    }
 }
 
 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
@@ -118,14 +120,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed)
     RCC_OscInitTypeDef RCC_OscInitStruct = {0};
     RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-    // If we are reconfiguring the clock, select CSI as system clock source to allow modification of the PLL configuration 
+    // If we are reconfiguring the clock, select CSI as system clock source to allow modification of the PLL configuration
     if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) {
-      RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-      RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_CSI;
-      if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-      {
-        return 0;
-      }
+        RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+        RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_CSI;
+        if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+            return 0;
+        }
     }
 
     /* Enable oscillator pin */
@@ -148,9 +149,9 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed)
     /* Configure the main internal regulator output voltage */
 
     if (lowspeed) {
-      __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+        __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
     } else {
-      __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+        __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
     }
 
     while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
@@ -167,17 +168,17 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed)
     RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
     RCC_OscInitStruct.PLL.PLLM = 5;
     if (lowspeed) {
-      RCC_OscInitStruct.PLL.PLLN = 40;
+        RCC_OscInitStruct.PLL.PLLN = 40;
     } else {
-      RCC_OscInitStruct.PLL.PLLN = 160;
+        RCC_OscInitStruct.PLL.PLLN = 160;
     }
 
 #if HSE_VALUE == 27000000
     RCC_OscInitStruct.PLL.PLLM = 9;
     if (lowspeed) {
-      RCC_OscInitStruct.PLL.PLLN = 80;
+        RCC_OscInitStruct.PLL.PLLN = 80;
     } else {
-      RCC_OscInitStruct.PLL.PLLN = 300;
+        RCC_OscInitStruct.PLL.PLLN = 300;
     }
 #endif
 
@@ -203,11 +204,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed)
     RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
     RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
     if (lowspeed) {
-      if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
-        return 0; // FAIL
+        if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) {
+            return 0;    // FAIL
+        }
     } else {
-      if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
-        return 0; // FAIL
+        if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+            return 0;    // FAIL
+        }
     }
 
     // HAL_RCCEx_EnableBootCore(RCC_BOOT_C2);
@@ -294,13 +297,13 @@ uint8_t SetSysClock_PLL_HSI(void)
 #if defined (CORE_CM4)
 void HSEM2_IRQHandler(void)
 {
-  HAL_HSEM_IRQHandler();
+    HAL_HSEM_IRQHandler();
 }
 #endif
 
 #if defined (CORE_CM7)
 void HSEM1_IRQHandler(void)
 {
-  HAL_HSEM_IRQHandler();
+    HAL_HSEM_IRQHandler();
 }
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L073xZ/system_clock.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L073xZ/system_clock.c
index ac0a5211084..919a9f76ba7 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L073xZ/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L073xZ/system_clock.c
@@ -104,7 +104,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
     /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_HSI48;
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
     if (bypass == 0) {
         RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
     } else {
diff --git a/targets/TARGET_STM/TARGET_STM32L0/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32L0/us_ticker_data.h
index 7dafadfae9c..5c6d27792a8 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/us_ticker_data.h
+++ b/targets/TARGET_STM/TARGET_STM32L0/us_ticker_data.h
@@ -17,7 +17,7 @@
 #define __US_TICKER_DATA_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 #include "stm32l0xx.h"
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xB/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xB/cmsis_nvic.h
index d67e5d3b111..605a4ee13e4 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xB/cmsis_nvic.h
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xB/cmsis_nvic.h
@@ -31,8 +31,8 @@
 
 #if !defined(MBED_RAM_SIZE)
 #define MBED_RAM_SIZE  0x8000  // 32 KB
- //   0x4000 // 16 KB STM32L151CB STM32L151RB STM32L151VB
- //   0x8000 // 32 KB STM32L151CBxxA STM32L151RBxxA STM32L151VBxxA
+//   0x4000 // 16 KB STM32L151CB STM32L151RB STM32L151VB
+//   0x8000 // 32 KB STM32L151CBxxA STM32L151RBxxA STM32L151VBxxA
 #warning "check MBED_RAM_SIZE value in cmsis_nvic.h"
 #endif
 
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xC/TARGET_XDOT_L151CC/system_clock.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xC/TARGET_XDOT_L151CC/system_clock.c
index 66a6421aebb..638e2f4b2cb 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xC/TARGET_XDOT_L151CC/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xC/TARGET_XDOT_L151CC/system_clock.c
@@ -63,7 +63,7 @@ uint8_t SetSysClock_PLL_HSI(void);
   * @param  None
   * @retval None
   */
-void SystemInit (void)
+void SystemInit(void)
 {
     /*!< Set MSION bit */
     RCC->CR |= (uint32_t)0x00000100;
@@ -131,7 +131,7 @@ void SetSysClock(void)
         {
             /* 3- If fail start with HSI clock */
             if (SetSysClock_PLL_HSI() == 0) {
-                while(1) {
+                while (1) {
                     // [TODO] Put something here to tell the user that a problem occured...
                 }
             }
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xB/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xB/cmsis_nvic.h
index 2220a436e8d..65294f7e490 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xB/cmsis_nvic.h
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xB/cmsis_nvic.h
@@ -31,8 +31,8 @@
 
 #if !defined(MBED_RAM_SIZE)
 #define MBED_RAM_SIZE  0x8000  // 32 KB
- //   0x4000 // 16 KB STM32L152CB STM32L152RB STM32L152VB
- //   0x8000 // 32 KB STM32L152CBxxA STM32L152RBxxA STM32L152VBxxA
+//   0x4000 // 16 KB STM32L152CB STM32L152RB STM32L152VB
+//   0x8000 // 32 KB STM32L152CBxxA STM32L152RBxxA STM32L152VBxxA
 #warning "check MBED_RAM_SIZE value in cmsis_nvic.h"
 #endif
 
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xC/TARGET_MOTE_L152RC/system_clock.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xC/TARGET_MOTE_L152RC/system_clock.c
index 9c66425f2be..b197f9418f0 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xC/TARGET_MOTE_L152RC/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xC/TARGET_MOTE_L152RC/system_clock.c
@@ -63,7 +63,7 @@ uint8_t SetSysClock_PLL_HSI(void);
   * @param  None
   * @retval None
   */
-void SystemInit (void)
+void SystemInit(void)
 {
     /*!< Set MSION bit */
     RCC->CR |= (uint32_t)0x00000100;
@@ -117,7 +117,7 @@ void SetSysClock(void)
         {
             /* 3- If fail start with HSI clock */
             if (SetSysClock_PLL_HSI() == 0) {
-                while(1) {
+                while (1) {
                     // [TODO] Put something here to tell the user that a problem occured...
                 }
             }
@@ -137,8 +137,9 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     RCC_ClkInitTypeDef RCC_ClkInitStruct;
     RCC_OscInitTypeDef RCC_OscInitStruct;
 
-    if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
-        return 1;   // already on HSE PLL, could occur from deepsleep waking
+    if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) {
+        return 1;    // already on HSE PLL, could occur from deepsleep waking
+    }
 
     /* Used to gain time after DeepSleep in case HSI is used */
     if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
diff --git a/targets/TARGET_STM/TARGET_STM32L1/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32L1/us_ticker_data.h
index 3cb73e3acaf..c32116dd87f 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/us_ticker_data.h
+++ b/targets/TARGET_STM/TARGET_STM32L1/us_ticker_data.h
@@ -17,13 +17,13 @@
 #define __US_TICKER_DATA_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 #include "stm32l1xx.h"
 #include "stm32l1xx_ll_tim.h"
 #include "cmsis_nvic.h"
-   
+
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L452xE/TARGET_NUCLEO_L452RE_P/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L452xE/TARGET_NUCLEO_L452RE_P/PeripheralPins.c
index 92cdf8990a0..cef7824a581 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L452xE/TARGET_NUCLEO_L452RE_P/PeripheralPins.c
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L452xE/TARGET_NUCLEO_L452RE_P/PeripheralPins.c
@@ -170,12 +170,12 @@ MBED_WEAK const PinMap PinMap_PWM[] = {
 MBED_WEAK const PinMap PinMap_UART_TX[] = {
     {PA_0,       UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
     {PA_2,       UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX
-    {PA_2_ALT0,  LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX
+    {PA_2_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX
     {PA_9,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_6,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_10,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-    {PB_11,      LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
-    {PC_1,       LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_11,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_1,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {PC_4,       UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     {PC_10,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     {PC_10_ALT0, UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
@@ -185,13 +185,13 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = {
 MBED_WEAK const PinMap PinMap_UART_RX[] = {
     {PA_1,       UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
     {PA_3,       UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX
-    {PA_3_ALT0,  LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_RX
+    {PA_3_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_RX
     {PA_10,      UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PA_15,      UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)},
     {PB_7,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PB_10,      LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_10,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {PB_11,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-    {PC_0,       LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_0,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {PC_11,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     {PC_11_ALT0, UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
     {NC, NC, 0}
@@ -203,9 +203,9 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = {
     {PA_15,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     {PA_15_ALT0, UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
     {PB_1,       UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-    {PB_1_ALT0,  LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_1_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {PB_3,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PB_12,      LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_12,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {PB_14,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     {NC, NC, 0}
 };
@@ -213,12 +213,12 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = {
 MBED_WEAK const PinMap PinMap_UART_CTS[] = {
     {PA_0,       UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {PA_6,       UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SMPS_PG [ADP5301ACBZ_OUTOK]
-    {PA_6_ALT0,  LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SMPS_PG [ADP5301ACBZ_OUTOK]
+    {PA_6_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SMPS_PG [ADP5301ACBZ_OUTOK]
     {PA_11,      UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_4,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_7,       UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
     {PB_13,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD4 [green Led]
-    {PB_13_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD4 [green Led]
+    {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD4 [green Led]
     {NC, NC, 0}
 };
 
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4S5xI/TARGET_B_L4S5I_IOT01A/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4S5xI/TARGET_B_L4S5I_IOT01A/PinNames.h
index 0b92191285e..f130662ac1e 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4S5xI/TARGET_B_L4S5I_IOT01A/PinNames.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4S5xI/TARGET_B_L4S5I_IOT01A/PinNames.h
@@ -234,7 +234,7 @@ typedef enum {
     SYS_WKUP4 = PA_2,
     SYS_WKUP5 = PC_5,
 
-   /**** QSPI FLASH pins ****/
+    /**** QSPI FLASH pins ****/
     QSPI_FLASH1_IO0 = PE_12,
     QSPI_FLASH1_IO1 = PE_13,
     QSPI_FLASH1_IO2 = PE_14,
diff --git a/targets/TARGET_STM/TARGET_STM32L4/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32L4/us_ticker_data.h
index 42d9bad21e9..fa83d6b2a03 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/us_ticker_data.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/us_ticker_data.h
@@ -19,7 +19,7 @@
 #define __US_TICKER_DATA_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 #include "stm32l4xx.h"
diff --git a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xE/TARGET_DISCO_L562QE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xE/TARGET_DISCO_L562QE/PeripheralPins.c
index dee2ebf67cc..4772207b1dd 100644
--- a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xE/TARGET_DISCO_L562QE/PeripheralPins.c
+++ b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xE/TARGET_DISCO_L562QE/PeripheralPins.c
@@ -294,7 +294,7 @@ MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
     {PA_7,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to OCTOSPI1_IO2
     {PA_12,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to USB_DP
     {PB_5_ALT0,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to UCPD_DBn
-    {PB_5     ,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to UCPD_DBn
+    {PB_5,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},      // Connected to UCPD_DBn
     {PB_15,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to UCPD1_CC2
     {PC_1,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_SPI2)}, // Connected to OCTOSPI1_IO4
     {PC_3,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to OCTOSPI1_IO6
@@ -310,7 +310,7 @@ MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
     {PA_6,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to OCTOSPI1_IO3
     {PA_11,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to USB_DM
     {PB_4_ALT0,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
-    {PB_4     ,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+    {PB_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
     {PB_14,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to UCPD_FLT
     {PC_2,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to OCTOSPI1_IO5
     {PC_11,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SDMMC1_D3
diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TARGET_DISCO_WB5MMG/PinNames.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TARGET_DISCO_WB5MMG/PinNames.h
index fe26e9982d4..94a74c40d4c 100644
--- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TARGET_DISCO_WB5MMG/PinNames.h
+++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TARGET_DISCO_WB5MMG/PinNames.h
@@ -127,12 +127,12 @@ typedef enum {
     ARDUINO_UNO_D7 = PB_2,
     ARDUINO_UNO_D8 = PD_13,
     ARDUINO_UNO_D9 = PD_15,
-    ARDUINO_UNO_D10= PA_4,
-    ARDUINO_UNO_D11= PA_7,
-    ARDUINO_UNO_D12= PB_4,
-    ARDUINO_UNO_D13= PA_1,
-    ARDUINO_UNO_D14= PA_10,
-    ARDUINO_UNO_D15= PB_8,
+    ARDUINO_UNO_D10 = PA_4,
+    ARDUINO_UNO_D11 = PA_7,
+    ARDUINO_UNO_D12 = PB_4,
+    ARDUINO_UNO_D13 = PA_1,
+    ARDUINO_UNO_D14 = PA_10,
+    ARDUINO_UNO_D15 = PB_8,
 #endif
 
     // STDIO for console print
@@ -186,8 +186,8 @@ typedef enum {
 
 // Standardized LED and button names
 #define LED1     PA_7  // LD4 is a RGB LED connected to a PWM LED driver // TODO
-#define BUTTON1  PC_12  
-#define BUTTON2  PC_13  
+#define BUTTON1  PC_12
+#define BUTTON2  PC_13
 
 #ifdef __cplusplus
 }
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/PeripheralNames.h
index 3a95d6d25d9..3971fb445f0 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/PeripheralNames.h
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/PeripheralNames.h
@@ -35,7 +35,7 @@ typedef enum {
 
 typedef enum {
     UART_1 = (int)USART1_BASE,
-	UART_2 = (int)USART2_BASE,
+    UART_2 = (int)USART2_BASE,
     LPUART_1 = (int)LPUART1_BASE
 } UARTName;
 
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/system_clock.c b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/system_clock.c
index ae2309a02a5..70d39202503 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/system_clock.c
@@ -39,31 +39,31 @@
 
 MBED_WEAK void SetSysClock(void)
 {
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Configure the main internal regulator output voltage
-  */
-  __HAL_RCC_PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the CPU, AHB and APB busses clocks
-  */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
-  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
-  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
-  MBED_ASSERT(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK);
-  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
-  */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK3|RCC_CLOCKTYPE_HCLK
-                              |RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
-                              |RCC_CLOCKTYPE_PCLK2;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1;
-  MBED_ASSERT(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) == HAL_OK);
-  /* Peripheral clock enable */
+    /** Configure the main internal regulator output voltage
+    */
+    __HAL_RCC_PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+    /** Initializes the CPU, AHB and APB busses clocks
+    */
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
+    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+    MBED_ASSERT(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK);
+    /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
+    */
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK3 | RCC_CLOCKTYPE_HCLK
+                                  | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1
+                                  | RCC_CLOCKTYPE_PCLK2;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+    RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1;
+    MBED_ASSERT(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) == HAL_OK);
+    /* Peripheral clock enable */
 }
diff --git a/targets/TARGET_STM/TARGET_STM32WL/serial_device.c b/targets/TARGET_STM/TARGET_STM32WL/serial_device.c
index b2377cb628c..ed6023fc46e 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/serial_device.c
+++ b/targets/TARGET_STM/TARGET_STM32WL/serial_device.c
@@ -125,7 +125,7 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
             __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
             // Check if RxIrq is disabled too
             if ((huart->Instance->CR1 & USART_CR1_RXNEIE_RXFNEIE) == 0) {
-				
+
                 all_disabled = 1;
             }
         }
diff --git a/targets/TARGET_STM/USBPhy_STM32.cpp b/targets/TARGET_STM/USBPhy_STM32.cpp
index 20eaa38278e..c412ea84a13 100644
--- a/targets/TARGET_STM/USBPhy_STM32.cpp
+++ b/targets/TARGET_STM/USBPhy_STM32.cpp
@@ -250,13 +250,13 @@ void USBPhyHw::init(USBPhyEvents *events)
 
     __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
 
-    #ifdef __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE
-        __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE();
-    #endif
-    #ifdef __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE
-        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE();
-    #endif
-     
+#ifdef __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE
+    __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE();
+#endif
+#ifdef __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE
+    __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE();
+#endif
+
     map = PinMap_USB_HS;
 
 #elif (MBED_CONF_TARGET_USB_SPEED == USE_USB_OTG_FS)
@@ -267,13 +267,13 @@ void USBPhyHw::init(USBPhyEvents *events)
 
     __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
-    #ifdef __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE
-        __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE();
-    #endif
-    #ifdef __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE
-        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE();
-    #endif
-     
+#ifdef __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE
+    __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE();
+#endif
+#ifdef __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE
+    __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE();
+#endif
+
     map = PinMap_USB_FS;
 
 #elif (MBED_CONF_TARGET_USB_SPEED == USE_USB_NO_OTG)
diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c
index abfff56496f..5463142fa3c 100644
--- a/targets/TARGET_STM/can_api.c
+++ b/targets/TARGET_STM/can_api.c
@@ -142,13 +142,13 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz
     // !When the sample point should be lower than 50%, this must be changed to
     // !IS_FDCAN_NOMINAL_TSEG2(ntq/nominalPrescaler), since
     // NTSEG2 and SJW max values are lower. For now the sample point is fix @75%
-    while (!IS_FDCAN_NOMINAL_TSEG1(ntq/nominalPrescaler)){
+    while (!IS_FDCAN_NOMINAL_TSEG1(ntq / nominalPrescaler)) {
         nominalPrescaler ++;
-        if (!IS_FDCAN_NOMINAL_PRESCALER(nominalPrescaler)){
+        if (!IS_FDCAN_NOMINAL_PRESCALER(nominalPrescaler)) {
             error("Could not determine good nominalPrescaler. Bad clock value\n");
         }
     }
-    ntq = ntq/nominalPrescaler;
+    ntq = ntq / nominalPrescaler;
 
     obj->CanHandle.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
     obj->CanHandle.Init.Mode = FDCAN_MODE_NORMAL;
@@ -298,13 +298,13 @@ int can_frequency(can_t *obj, int f)
     // !When the sample point should be lower than 50%, this must be changed to
     // !IS_FDCAN_DATA_TSEG2(ntq/nominalPrescaler), since
     // NTSEG2 and SJW max values are lower. For now the sample point is fix @75%
-    while (!IS_FDCAN_DATA_TSEG1(ntq/nominalPrescaler)){
+    while (!IS_FDCAN_DATA_TSEG1(ntq / nominalPrescaler)) {
         nominalPrescaler ++;
-        if (!IS_FDCAN_NOMINAL_PRESCALER(nominalPrescaler)){
+        if (!IS_FDCAN_NOMINAL_PRESCALER(nominalPrescaler)) {
             error("Could not determine good nominalPrescaler. Bad clock value\n");
         }
     }
-    ntq = ntq/nominalPrescaler;
+    ntq = ntq / nominalPrescaler;
 
     obj->CanHandle.Init.NominalPrescaler = nominalPrescaler;
     obj->CanHandle.Init.NominalTimeSeg1 = ntq * 0.75;      // Phase_segment_1
@@ -596,7 +596,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
 #ifndef TARGET_STM32G4
             interrupts = FDCAN_IT_RX_BUFFER_NEW_MESSAGE;
 #else
-	    interrupts = FDCAN_IT_RX_FIFO0_NEW_MESSAGE;
+            interrupts = FDCAN_IT_RX_FIFO0_NEW_MESSAGE;
 #endif
             break;
         case IRQ_ERROR:
@@ -1102,7 +1102,7 @@ int can_mode(can_t *obj, CanMode mode)
 int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle)
 {
     int success = 0;
-    
+
     // filter for CANAny format cannot be configured for STM32
     if ((format == CANStandard) || (format == CANExtended)) {
         CAN_FilterConfTypeDef  sFilterConfig;
@@ -1126,8 +1126,7 @@ int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t
         sFilterConfig.FilterActivation = ENABLE;
         sFilterConfig.BankNumber = 14;
 
-        if (HAL_CAN_ConfigFilter(&obj->CanHandle, &sFilterConfig) == HAL_OK)
-        {
+        if (HAL_CAN_ConfigFilter(&obj->CanHandle, &sFilterConfig) == HAL_OK) {
             success = 1;
         }
     }
diff --git a/targets/TARGET_STM/hal_tick_overrides.c b/targets/TARGET_STM/hal_tick_overrides.c
index c12c84df8e2..f12f79da596 100644
--- a/targets/TARGET_STM/hal_tick_overrides.c
+++ b/targets/TARGET_STM/hal_tick_overrides.c
@@ -71,7 +71,7 @@ uint32_t HAL_GetTick()
         prev_tick_remainder = elapsed_time % 1000;
     }
     total_ticks += elapsed_ticks;
-    
+
     core_util_critical_section_exit();
     return total_ticks;
 }
diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c
index 4774ede0cbc..964b508cee7 100644
--- a/targets/TARGET_STM/lp_ticker.c
+++ b/targets/TARGET_STM/lp_ticker.c
@@ -285,7 +285,7 @@ void lp_ticker_init(void)
 
 #if (LPTIM_MST_BASE == LPTIM1_BASE)
 #if defined (__HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT)
-__HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT();
+    __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT();
 #endif
 #endif
 #if defined (__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT)
diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c
index 5647d971329..f5e1e6c6149 100644
--- a/targets/TARGET_STM/mbed_overrides.c
+++ b/targets/TARGET_STM/mbed_overrides.c
@@ -41,30 +41,31 @@ extern void SetSysClock(void);
 
 /**
  * @brief configure the LSE crystal driver load
- * This settings ist target hardware dependend and 
+ * This setting is target hardware dependend and
  * depends on the crystal that is used for LSE clock.
  * For low power requirements, crystals with low load capacitors can be used and
  * driver setting is RCC_LSEDRIVE_LOW.
  * For higher stablity, crystals with higher load capacitys can be used and
  * driver setting is RCC_LSEDRIVE_HIGH.
- * 
+ *
  * A detailed description about this setting can be found here:
  * https://www.st.com/resource/en/application_note/cd00221665-oscillator-design-guide-for-stm8afals-stm32-mcus-and-mpus-stmicroelectronics.pdf
- * 
- * LSE maybe used later, but crystal load drive setting is necessary before 
+ *
+ * LSE maybe used later, but crystal load drive setting is necessary before
  * enabling LSE.
- *   
+ *
  * @param None
  * @retval None
  */
 
-static void LSEDriveConfig(void) {
+static void LSEDriveConfig(void)
+{
     HAL_PWR_EnableBkUpAccess();
-    #if defined(__HAL_RCC_LSEDRIVE_CONFIG)
-        __HAL_RCC_LSEDRIVE_CONFIG(LSE_DRIVE_LOAD_LEVEL);
-    #else
-        HAL_RCCEx_SelectLSEMode(LSE_DRIVE_LOAD_LEVEL);
-    #endif
+#if defined(__HAL_RCC_LSEDRIVE_CONFIG)
+    __HAL_RCC_LSEDRIVE_CONFIG(LSE_DRIVE_LOAD_LEVEL);
+#else
+    HAL_RCCEx_SelectLSEMode(LSE_DRIVE_LOAD_LEVEL);
+#endif
 }
 #endif  // LSE_CONFIG_AVAILABLE
 
@@ -79,13 +80,15 @@ static void LSEDriveConfig(void) {
  * @param None
  * @retval None
  */
-MBED_WEAK void TargetBSP_Init(void) {
+MBED_WEAK void TargetBSP_Init(void)
+{
     /** Do nothing */
 }
 
 #ifndef MBED_DEBUG
 #if MBED_CONF_TARGET_GPIO_RESET_AT_INIT
-void GPIO_Full_Init(void) {
+void GPIO_Full_Init(void)
+{
     GPIO_InitTypeDef GPIO_InitStruct;
 
     GPIO_InitStruct.Pin        = GPIO_PIN_All;
@@ -238,7 +241,7 @@ void mbed_sdk_init()
 #if IS_PWR_SUPPLY(MBED_CONF_TARGET_SYSTEM_POWER_SUPPLY)
     HAL_PWREx_ConfigSupply(MBED_CONF_TARGET_SYSTEM_POWER_SUPPLY);
 #else
-    #error system_power_supply not configured
+#error system_power_supply not configured
 #endif
 #endif
 
@@ -276,7 +279,7 @@ void mbed_sdk_init()
 #if IS_PWR_SUPPLY(MBED_CONF_TARGET_SYSTEM_POWER_SUPPLY)
     HAL_PWREx_ConfigSupply(MBED_CONF_TARGET_SYSTEM_POWER_SUPPLY);
 #else
-    #error system_power_supply not configured
+#error system_power_supply not configured
 #endif
 #endif
 
@@ -290,8 +293,7 @@ void mbed_sdk_init()
     RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
     PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
     PeriphClkInitStruct.RTCClockSelection = (RCC_RTCCLKSOURCE_HSE_DIVX | RTC_HSE_DIV << 16);
-    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
-    {
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
         error("PeriphClkInitStruct RTC failed with HSE\n");
     }
 #elif ((MBED_CONF_TARGET_RTC_CLOCK_SOURCE == USE_RTC_CLK_LSE_OR_LSI) && !MBED_CONF_TARGET_LSE_AVAILABLE) || (MBED_CONF_TARGET_RTC_CLOCK_SOURCE == USE_RTC_CLK_LSI)
diff --git a/targets/TARGET_STM/ospi_api.c b/targets/TARGET_STM/ospi_api.c
index bd9df34748e..5b5746b5f0f 100644
--- a/targets/TARGET_STM/ospi_api.c
+++ b/targets/TARGET_STM/ospi_api.c
@@ -65,7 +65,7 @@ ospi_status_t ospi_prepare_command(const ospi_command_t *command, OSPI_RegularCm
         st_command->Instruction = 0;
     } else {
         st_command->Instruction = ((command->instruction.bus_width == OSPI_CFG_BUS_OCTA) || (command->instruction.bus_width == OSPI_CFG_BUS_OCTA_DTR))
-		                            ? command->instruction.value << 8 | (0xFF - command->instruction.value) : command->instruction.value;
+                                  ? command->instruction.value << 8 | (0xFF - command->instruction.value) : command->instruction.value;
         switch (command->instruction.bus_width) {
             case OSPI_CFG_BUS_SINGLE:
                 st_command->InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
@@ -87,14 +87,14 @@ ospi_status_t ospi_prepare_command(const ospi_command_t *command, OSPI_RegularCm
     }
 
     st_command->InstructionSize    = (st_command->InstructionMode == HAL_OSPI_INSTRUCTION_8_LINES) ? HAL_OSPI_INSTRUCTION_16_BITS : HAL_OSPI_INSTRUCTION_8_BITS;
-    st_command->InstructionDtrMode = (command->instruction.bus_width == OSPI_CFG_BUS_OCTA_DTR) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE :HAL_OSPI_INSTRUCTION_DTR_DISABLE;
+    st_command->InstructionDtrMode = (command->instruction.bus_width == OSPI_CFG_BUS_OCTA_DTR) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
     st_command->DummyCycles = command->dummy_count;
     // these are target specific settings, use default values
     st_command->SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
     st_command->DataDtrMode = (command->instruction.bus_width == OSPI_CFG_BUS_OCTA_DTR) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE;
     st_command->AddressDtrMode = (command->instruction.bus_width == OSPI_CFG_BUS_OCTA_DTR) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE;
     st_command->AlternateBytesDtrMode = (command->instruction.bus_width == OSPI_CFG_BUS_OCTA_DTR) ? HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE : HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE;
-    st_command->DQSMode = (command->instruction.bus_width == OSPI_CFG_BUS_OCTA_DTR) ? HAL_OSPI_DQS_ENABLE :HAL_OSPI_DQS_DISABLE;
+    st_command->DQSMode = (command->instruction.bus_width == OSPI_CFG_BUS_OCTA_DTR) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE;
 
     st_command->OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
     if (command->address.disabled == true) {
@@ -245,7 +245,7 @@ static ospi_status_t _ospi_init_direct(ospi_t *obj, const ospi_pinmap_t *pinmap,
     // Set default OCTOSPI handle values
     obj->handle.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE;
 //#if defined(TARGET_MX25LM512451G)
- //   obj->handle.Init.MemoryType = HAL_OSPI_MEMTYPE_MACRONIX; // Read sequence in DTR mode: D1-D0-D3-D2
+//   obj->handle.Init.MemoryType = HAL_OSPI_MEMTYPE_MACRONIX; // Read sequence in DTR mode: D1-D0-D3-D2
 //#else
     obj->handle.Init.MemoryType = HAL_OSPI_MEMTYPE_MICRON;   // Read sequence in DTR mode: D0-D1-D2-D3
 //#endif
@@ -365,7 +365,7 @@ static ospi_status_t _ospi_init_direct(ospi_t *obj, const ospi_pinmap_t *pinmap,
 }
 
 ospi_status_t ospi_init(ospi_t *obj, PinName io0, PinName io1, PinName io2, PinName io3, PinName io4, PinName io5, PinName io6, PinName io7,
-			PinName sclk, PinName ssel, PinName dqs, uint32_t hz, uint8_t mode)
+                        PinName sclk, PinName ssel, PinName dqs, uint32_t hz, uint8_t mode)
 {
     OSPIName ospiio0name = (OSPIName)pinmap_peripheral(io0, PinMap_OSPI_DATA0);
     OSPIName ospiio1name = (OSPIName)pinmap_peripheral(io1, PinMap_OSPI_DATA1);
@@ -403,8 +403,9 @@ ospi_status_t ospi_init(ospi_t *obj, PinName io0, PinName io1, PinName io2, PinN
     int function_dqs = (int)pinmap_find_function(dqs, PinMap_OSPI_DQS);
 
     const ospi_pinmap_t static_pinmap = {peripheral, io0, function_io0, io1, function_io1, io2, function_io2, io3, function_io3,
-    		                             io4, function_io4, io5, function_io5, io6, function_io6, io7, function_io7,
-    		                             sclk, function_sclk, ssel, function_ssel, dqs, function_dqs};
+                                         io4, function_io4, io5, function_io5, io6, function_io6, io7, function_io7,
+                                         sclk, function_sclk, ssel, function_ssel, dqs, function_dqs
+                                        };
 
     return OSPI_INIT_DIRECT(obj, &static_pinmap, hz, mode);
 }
diff --git a/targets/TARGET_STM/serial_api.c b/targets/TARGET_STM/serial_api.c
index 259c7b8719b..d905aceb4d9 100644
--- a/targets/TARGET_STM/serial_api.c
+++ b/targets/TARGET_STM/serial_api.c
@@ -354,10 +354,10 @@ void serial_free(serial_t *obj)
     pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0));
     pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0));
 #if DEVICE_SERIAL_FC
-    if ( (obj_s->hw_flow_ctl == UART_HWCONTROL_RTS) || (obj_s->hw_flow_ctl == UART_HWCONTROL_RTS_CTS) ) {
+    if ((obj_s->hw_flow_ctl == UART_HWCONTROL_RTS) || (obj_s->hw_flow_ctl == UART_HWCONTROL_RTS_CTS)) {
         pin_function(obj_s->pin_rts, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0));
     }
-    if ( (obj_s->hw_flow_ctl == UART_HWCONTROL_CTS) || (obj_s->hw_flow_ctl == UART_HWCONTROL_RTS_CTS) ) {
+    if ((obj_s->hw_flow_ctl == UART_HWCONTROL_CTS) || (obj_s->hw_flow_ctl == UART_HWCONTROL_RTS_CTS)) {
         pin_function(obj_s->pin_cts, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0));
     }
 #endif
diff --git a/targets/TARGET_STM/sleep.c b/targets/TARGET_STM/sleep.c
index df923808139..b266c74c70a 100644
--- a/targets/TARGET_STM/sleep.c
+++ b/targets/TARGET_STM/sleep.c
@@ -181,7 +181,7 @@ __WEAK void hal_deepsleep(void)
     save_timer_ctx();
 
     // Request to enter STOP mode with regulator in low power mode
-	//PWR_CR1_LPMS_STOP2 -> STM32L4 ; PWR_LOWPOWERMODE_STOP2 -> STM32WL
+    //PWR_CR1_LPMS_STOP2 -> STM32L4 ; PWR_LOWPOWERMODE_STOP2 -> STM32WL
 #if defined (PWR_CR1_LPMS_STOP2) || defined(PWR_LOWPOWERMODE_STOP2)
     int pwrClockEnabled = __HAL_RCC_PWR_IS_CLK_ENABLED();
     int lowPowerModeEnabled = PWR->CR1 & PWR_CR1_LPR;
diff --git a/targets/TARGET_STM/stm_spi_api.c b/targets/TARGET_STM/stm_spi_api.c
index 2c891635e44..1b3b16be385 100644
--- a/targets/TARGET_STM/stm_spi_api.c
+++ b/targets/TARGET_STM/stm_spi_api.c
@@ -400,132 +400,132 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
             DataSize = SPI_DATASIZE_4BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_5BIT)        
+#if defined(SPI_DATASIZE_5BIT)
         case 5:
             DataSize = SPI_DATASIZE_5BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_6BIT)        
+#if defined(SPI_DATASIZE_6BIT)
         case 6:
             DataSize = SPI_DATASIZE_6BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_7BIT)        
+#if defined(SPI_DATASIZE_7BIT)
         case 7:
             DataSize = SPI_DATASIZE_7BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_9BIT)        
+#if defined(SPI_DATASIZE_9BIT)
         case 9:
             DataSize = SPI_DATASIZE_9BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_10BIT)        
+#if defined(SPI_DATASIZE_10BIT)
         case 10:
             DataSize = SPI_DATASIZE_10BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_11BIT)        
+#if defined(SPI_DATASIZE_11BIT)
         case 11:
             DataSize = SPI_DATASIZE_11BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_12BIT)        
+#if defined(SPI_DATASIZE_12BIT)
         case 12:
             DataSize = SPI_DATASIZE_12BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_13BIT)        
+#if defined(SPI_DATASIZE_13BIT)
         case 13:
             DataSize = SPI_DATASIZE_13BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_14BIT)        
+#if defined(SPI_DATASIZE_14BIT)
         case 14:
             DataSize = SPI_DATASIZE_14BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_15BIT)        
+#if defined(SPI_DATASIZE_15BIT)
         case 15:
             DataSize = SPI_DATASIZE_15BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_17BIT)        
+#if defined(SPI_DATASIZE_17BIT)
         case 17:
             DataSize = SPI_DATASIZE_17BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_18BIT)        
+#if defined(SPI_DATASIZE_18BIT)
         case 18:
             DataSize = SPI_DATASIZE_18BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_19BIT)        
+#if defined(SPI_DATASIZE_19BIT)
         case 19:
             DataSize = SPI_DATASIZE_19BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_20BIT)        
+#if defined(SPI_DATASIZE_20BIT)
         case 20:
             DataSize = SPI_DATASIZE_20BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_21BIT)        
+#if defined(SPI_DATASIZE_21BIT)
         case 21:
             DataSize = SPI_DATASIZE_21BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_22BIT)        
+#if defined(SPI_DATASIZE_22BIT)
         case 22:
             DataSize = SPI_DATASIZE_22BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_23BIT)        
+#if defined(SPI_DATASIZE_23BIT)
         case 23:
             DataSize = SPI_DATASIZE_23BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_24BIT)        
+#if defined(SPI_DATASIZE_24BIT)
         case 24:
             DataSize = SPI_DATASIZE_24BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_25BIT)        
+#if defined(SPI_DATASIZE_25BIT)
         case 25:
             DataSize = SPI_DATASIZE_25BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_26BIT)        
+#if defined(SPI_DATASIZE_26BIT)
         case 26:
             DataSize = SPI_DATASIZE_26BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_27BIT)        
+#if defined(SPI_DATASIZE_27BIT)
         case 27:
             DataSize = SPI_DATASIZE_27BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_28BIT)        
+#if defined(SPI_DATASIZE_28BIT)
         case 28:
             DataSize = SPI_DATASIZE_28BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_29BIT)        
+#if defined(SPI_DATASIZE_29BIT)
         case 29:
             DataSize = SPI_DATASIZE_29BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_30BIT)        
+#if defined(SPI_DATASIZE_30BIT)
         case 30:
             DataSize = SPI_DATASIZE_30BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_31BIT)        
+#if defined(SPI_DATASIZE_31BIT)
         case 31:
             DataSize = SPI_DATASIZE_31BIT;
             break;
 #endif
-#if defined(SPI_DATASIZE_32BIT)        
+#if defined(SPI_DATASIZE_32BIT)
         case 32:
             DataSize = SPI_DATASIZE_32BIT;
             break;
@@ -667,106 +667,107 @@ static inline int ssp_busy(spi_t *obj)
     return status;
 }
 
-static inline int datasize_to_transfer_bitshift(uint32_t DataSize) {
+static inline int datasize_to_transfer_bitshift(uint32_t DataSize)
+{
     switch (DataSize) {
 #if defined(SPI_DATASIZE_4BIT)
         case SPI_DATASIZE_4BIT:
 #endif
-#if defined(SPI_DATASIZE_5BIT)        
+#if defined(SPI_DATASIZE_5BIT)
         case SPI_DATASIZE_5BIT:
 #endif
-#if defined(SPI_DATASIZE_6BIT)        
+#if defined(SPI_DATASIZE_6BIT)
         case SPI_DATASIZE_6BIT:
 #endif
-#if defined(SPI_DATASIZE_7BIT)        
+#if defined(SPI_DATASIZE_7BIT)
         case SPI_DATASIZE_7BIT:
 #endif
         case SPI_DATASIZE_8BIT:
             return 0;
-#if defined(SPI_DATASIZE_9BIT)        
+#if defined(SPI_DATASIZE_9BIT)
         case SPI_DATASIZE_9BIT:
 #endif
-#if defined(SPI_DATASIZE_10BIT)        
+#if defined(SPI_DATASIZE_10BIT)
         case SPI_DATASIZE_10BIT:
 #endif
-#if defined(SPI_DATASIZE_11BIT)        
+#if defined(SPI_DATASIZE_11BIT)
         case SPI_DATASIZE_11BIT:
 #endif
-#if defined(SPI_DATASIZE_12BIT)        
+#if defined(SPI_DATASIZE_12BIT)
         case SPI_DATASIZE_12BIT:
 #endif
-#if defined(SPI_DATASIZE_13BIT)        
+#if defined(SPI_DATASIZE_13BIT)
         case SPI_DATASIZE_13BIT:
 #endif
-#if defined(SPI_DATASIZE_14BIT)        
+#if defined(SPI_DATASIZE_14BIT)
         case SPI_DATASIZE_14BIT:
 #endif
-#if defined(SPI_DATASIZE_15BIT)        
+#if defined(SPI_DATASIZE_15BIT)
         case SPI_DATASIZE_15BIT:
 #endif
         case SPI_DATASIZE_16BIT:
             return 1;
-#if defined(SPI_DATASIZE_17BIT)        
+#if defined(SPI_DATASIZE_17BIT)
         case SPI_DATASIZE_17BIT:
             return 2;
 #endif
-#if defined(SPI_DATASIZE_18BIT)        
+#if defined(SPI_DATASIZE_18BIT)
         case SPI_DATASIZE_18BIT:
             return 2;
 #endif
-#if defined(SPI_DATASIZE_19BIT)        
+#if defined(SPI_DATASIZE_19BIT)
         case SPI_DATASIZE_19BIT:
             return 2;
 #endif
-#if defined(SPI_DATASIZE_20BIT)        
+#if defined(SPI_DATASIZE_20BIT)
         case SPI_DATASIZE_20BIT:
             return 2;
 #endif
-#if defined(SPI_DATASIZE_21BIT)        
+#if defined(SPI_DATASIZE_21BIT)
         case SPI_DATASIZE_21BIT:
             return 2;
 #endif
-#if defined(SPI_DATASIZE_22BIT)        
+#if defined(SPI_DATASIZE_22BIT)
         case SPI_DATASIZE_22BIT:
             return 2;
 #endif
-#if defined(SPI_DATASIZE_23BIT)        
+#if defined(SPI_DATASIZE_23BIT)
         case SPI_DATASIZE_23BIT:
             return 2;
 #endif
-#if defined(SPI_DATASIZE_24BIT)        
+#if defined(SPI_DATASIZE_24BIT)
         case SPI_DATASIZE_24BIT:
             return 2;
 #endif
-#if defined(SPI_DATASIZE_25BIT)        
+#if defined(SPI_DATASIZE_25BIT)
         case SPI_DATASIZE_25BIT:
             return 2;
 #endif
-#if defined(SPI_DATASIZE_26BIT)        
+#if defined(SPI_DATASIZE_26BIT)
         case SPI_DATASIZE_26BIT:
             return 2;
 #endif
-#if defined(SPI_DATASIZE_27BIT)        
+#if defined(SPI_DATASIZE_27BIT)
         case SPI_DATASIZE_27BIT:
             return 2;
 #endif
-#if defined(SPI_DATASIZE_28BIT)        
+#if defined(SPI_DATASIZE_28BIT)
         case SPI_DATASIZE_28BIT:
             return 2;
 #endif
-#if defined(SPI_DATASIZE_29BIT)        
+#if defined(SPI_DATASIZE_29BIT)
         case SPI_DATASIZE_29BIT:
             return 2;
 #endif
-#if defined(SPI_DATASIZE_30BIT)        
+#if defined(SPI_DATASIZE_30BIT)
         case SPI_DATASIZE_30BIT:
             return 2;
 #endif
-#if defined(SPI_DATASIZE_31BIT)        
+#if defined(SPI_DATASIZE_31BIT)
         case SPI_DATASIZE_31BIT:
             return 2;
 #endif
-#if defined(SPI_DATASIZE_32BIT)        
+#if defined(SPI_DATASIZE_32BIT)
         case SPI_DATASIZE_32BIT:
             return 2;
 #endif