66* @version 1.0
77* @date 20. Nov. 2011
88* @author NXP MCU SW Application Team
9- *
9+ *
1010* Copyright(C) 2011, NXP Semiconductor
1111* All rights reserved.
1212*
6262
6363#if NO_SYS == 0
6464/** \brief Driver transmit and receive thread priorities
65- *
65+ *
6666 * Thread priorities for receive thread and TX cleanup thread. Alter
6767 * to prioritize receive or transmit bandwidth. In a heavily loaded
6868 * system or with LEIP_DEBUG enabled, the priorities might be better
7171#define TX_PRIORITY (osPriorityNormal)
7272
7373/** \brief Debug output formatter lock define
74- *
74+ *
7575 * When using FreeRTOS and with LWIP_DEBUG enabled, enabling this
7676 * define will allow RX debug messages to not interleave with the
7777 * TX messages (so they are actually readable). Not enabling this
@@ -144,7 +144,7 @@ struct lpc_enetdata {
144144
145145/** \brief LPC EMAC driver work data
146146 */
147- ETHMEM_SECTION struct lpc_enetdata lpc_enetdata ;
147+ ETHMEM_SECTION struct lpc_enetdata lpc_enetdata ;
148148
149149/* Write a value via the MII link (non-blocking) */
150150void lpc_mii_write_noblock (u32_t PhyReg , u32_t Value )
@@ -196,15 +196,15 @@ u32_t lpc_mii_read_data(void)
196196}
197197
198198/* Starts a read operation via the MII link (non-blocking) */
199- void lpc_mii_read_noblock (u32_t PhyReg )
199+ void lpc_mii_read_noblock (u32_t PhyReg )
200200{
201201 /* Read value at PHY address and register */
202202 LPC_EMAC -> MADR = (LPC_PHYDEF_PHYADDR << 8 ) | PhyReg ;
203203 LPC_EMAC -> MCMD = EMAC_MCMD_READ ;
204204}
205205
206206/* Read a value via the MII link (blocking) */
207- err_t lpc_mii_read (u32_t PhyReg , u32_t * data )
207+ err_t lpc_mii_read (u32_t PhyReg , u32_t * data )
208208{
209209 u32_t mst = 250 ;
210210 err_t sts = ERR_OK ;
@@ -307,7 +307,7 @@ s32_t lpc_rx_queue(struct netif *netif)
307307}
308308
309309/** \brief Sets up the RX descriptor ring buffers.
310- *
310+ *
311311 * This function sets up the descriptor list used for receive packets.
312312 *
313313 * \param[in] lpc_enetif Pointer to driver data structure
@@ -414,7 +414,7 @@ static struct pbuf *lpc_low_level_input(struct netif *netif)
414414 LWIP_DEBUGF (UDP_LPC_EMAC | LWIP_DBG_TRACE ,
415415 ("lpc_low_level_input: Packet dropped with errors (0x%x)\n" ,
416416 lpc_enetif -> prxs [idx ].statusinfo ));
417-
417+
418418 p = NULL ;
419419 } else {
420420 /* A packet is waiting, get length */
@@ -447,7 +447,7 @@ static struct pbuf *lpc_low_level_input(struct netif *netif)
447447#endif
448448#endif
449449
450- return p ;
450+ return p ;
451451}
452452
453453/** \brief Attempt to read a packet from the EMAC interface.
@@ -497,11 +497,11 @@ void lpc_enetif_input(struct netif *netif)
497497 */
498498static s32_t lpc_packet_addr_notsafe (void * addr ) {
499499 /* Check for legal address ranges */
500- #if defined(TARGET_LPC1768 )
500+ #if defined(TARGET_LPC1768 )
501501 if ((((u32_t ) addr >= 0x2007C000 ) && ((u32_t ) addr < 0x20083FFF ))) {
502502#elif defined(TARGET_LPC4088)
503503 if ((((u32_t ) addr >= 0x20000000 ) && ((u32_t ) addr < 0x20007FFF ))) {
504- #endif
504+ #endif
505505 return 0 ;
506506 }
507507 return 1 ;
@@ -641,7 +641,7 @@ static err_t lpc_low_level_output(struct netif *netif, struct pbuf *p)
641641 /* Allocate a pbuf in DMA memory */
642642 np = pbuf_alloc (PBUF_RAW , p -> tot_len , PBUF_RAM );
643643 if (np == NULL )
644- return ERR_MEM ;
644+ return ERR_MEM ;
645645
646646 /* This buffer better be contiguous! */
647647 LWIP_ASSERT ("lpc_low_level_output: New transmit pbuf is chained" ,
@@ -654,7 +654,7 @@ static err_t lpc_low_level_output(struct netif *netif, struct pbuf *p)
654654 MEMCPY (dst , (u8_t * ) q -> payload , q -> len );
655655 dst += q -> len ;
656656 }
657- np -> len = p -> tot_len ;
657+ np -> len = p -> tot_len ;
658658
659659 LWIP_DEBUGF (UDP_LPC_EMAC | LWIP_DBG_TRACE ,
660660 ("lpc_low_level_output: Switched to DMA safe buffer, old=%p, new=%p\n" ,
@@ -759,12 +759,12 @@ void ENET_IRQHandler(void)
759759 /* RX group interrupt(s): Give semaphore to wakeup RX receive task.*/
760760 sys_sem_signal (& lpc_enetdata .RxSem );
761761 }
762-
762+
763763 if (ints & TXINTGROUP ) {
764764 /* TX group interrupt(s): Give semaphore to wakeup TX cleanup task. */
765765 sys_sem_signal (& lpc_enetdata .TxCleanSem );
766766 }
767-
767+
768768 /* Clear pending interrupts */
769769 LPC_EMAC -> IntClear = ints ;
770770#endif
@@ -780,11 +780,11 @@ void ENET_IRQHandler(void)
780780 */
781781static void packet_rx (void * pvParameters ) {
782782 struct lpc_enetdata * lpc_enetif = pvParameters ;
783-
783+
784784 while (1 ) {
785785 /* Wait for receive task to wakeup */
786786 sys_arch_sem_wait (& lpc_enetif -> RxSem , 0 );
787-
787+
788788 /* Process packets until all empty */
789789 while (LPC_EMAC -> RxConsumeIndex != LPC_EMAC -> RxProduceIndex )
790790 lpc_enetif_input (lpc_enetif -> netif );
@@ -802,34 +802,34 @@ static void packet_rx(void* pvParameters) {
802802static void packet_tx (void * pvParameters ) {
803803 struct lpc_enetdata * lpc_enetif = pvParameters ;
804804 s32_t idx ;
805-
805+
806806 while (1 ) {
807807 /* Wait for transmit cleanup task to wakeup */
808808 sys_arch_sem_wait (& lpc_enetif -> TxCleanSem , 0 );
809-
809+
810810 /* Error handling for TX underruns. This should never happen unless
811811 something is holding the bus or the clocks are going too slow. It
812812 can probably be safely removed. */
813813 if (LPC_EMAC -> IntStatus & EMAC_INT_TX_UNDERRUN ) {
814814 LINK_STATS_INC (link .err );
815815 LINK_STATS_INC (link .drop );
816-
816+
817817#if NO_SYS == 0
818818 /* Get exclusive access */
819819 sys_mutex_lock (& lpc_enetif -> TXLockMutex );
820820#endif
821821 /* Reset the TX side */
822822 LPC_EMAC -> MAC1 |= EMAC_MAC1_RES_TX ;
823823 LPC_EMAC -> IntClear = EMAC_INT_TX_UNDERRUN ;
824-
824+
825825 /* De-allocate all queued TX pbufs */
826826 for (idx = 0 ; idx < LPC_NUM_BUFF_TXDESCS ; idx ++ ) {
827827 if (lpc_enetif -> txb [idx ] != NULL ) {
828828 pbuf_free (lpc_enetif -> txb [idx ]);
829829 lpc_enetif -> txb [idx ] = NULL ;
830830 }
831831 }
832-
832+
833833#if NO_SYS == 0
834834 /* Restore access */
835835 sys_mutex_unlock (& lpc_enetif -> TXLockMutex );
@@ -855,8 +855,8 @@ static err_t low_level_init(struct netif *netif)
855855
856856 /* Enable MII clocking */
857857 LPC_SC -> PCONP |= CLKPWR_PCONP_PCENET ;
858-
859- #if defined(TARGET_LPC1768 )
858+
859+ #if defined(TARGET_LPC1768 )
860860 LPC_PINCON -> PINSEL2 = 0x50150105 ; /* Enable P1 Ethernet Pins. */
861861 LPC_PINCON -> PINSEL3 = (LPC_PINCON -> PINSEL3 & ~0x0000000F ) | 0x00000005 ;
862862#elif defined(TARGET_LPC4088 )
@@ -880,16 +880,16 @@ static err_t low_level_init(struct netif *netif)
880880 LPC_IOCON -> P1_16 |= 0x01 ; /* ENET_MDC */
881881 LPC_IOCON -> P1_17 &= ~0x07 ;
882882 LPC_IOCON -> P1_17 |= 0x01 ; /* ENET_MDIO */
883- #endif
884-
883+ #endif
884+
885885 /* Reset all MAC logic */
886886 LPC_EMAC -> MAC1 = EMAC_MAC1_RES_TX | EMAC_MAC1_RES_MCS_TX |
887887 EMAC_MAC1_RES_RX | EMAC_MAC1_RES_MCS_RX | EMAC_MAC1_SIM_RES |
888888 EMAC_MAC1_SOFT_RES ;
889889 LPC_EMAC -> Command = EMAC_CR_REG_RES | EMAC_CR_TX_RES | EMAC_CR_RX_RES |
890890 EMAC_CR_PASS_RUNT_FRM ;
891891 osDelay (10 );
892-
892+
893893 /* Initial MAC initialization */
894894 LPC_EMAC -> MAC1 = EMAC_MAC1_PASS_ALL ;
895895 LPC_EMAC -> MAC2 = EMAC_MAC2_CRC_EN | EMAC_MAC2_PAD_EN |
@@ -980,7 +980,7 @@ void lpc_emac_set_speed(int mbs_100)
980980 *
981981 * \param[in] netif the lwip network interface structure for this lpc_enetif
982982 * \param[in] q Pointer to pbug to send
983- * \param[in] ipaddr IP address
983+ * \param[in] ipaddr IP address
984984 * \return ERR_OK or error code
985985 */
986986err_t lpc_etharp_output (struct netif * netif , struct pbuf * q ,
@@ -1017,11 +1017,20 @@ err_t lpc_enetif_init(struct netif *netif)
10171017 err_t err ;
10181018
10191019 LWIP_ASSERT ("netif != NULL" , (netif != NULL ));
1020-
1020+
10211021 lpc_enetdata .netif = netif ;
10221022
10231023 /* set MAC hardware address */
1024+ #if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE )
1025+ netif -> hwaddr [0 ] = MBED_MAC_ADDR_0 ;
1026+ netif -> hwaddr [1 ] = MBED_MAC_ADDR_1 ;
1027+ netif -> hwaddr [2 ] = MBED_MAC_ADDR_2 ;
1028+ netif -> hwaddr [3 ] = MBED_MAC_ADDR_3 ;
1029+ netif -> hwaddr [4 ] = MBED_MAC_ADDR_4 ;
1030+ netif -> hwaddr [5 ] = MBED_MAC_ADDR_5 ;
1031+ #else
10241032 mbed_mac_address ((char * )netif -> hwaddr );
1033+ #endif
10251034 netif -> hwaddr_len = ETHARP_HWADDR_LEN ;
10261035
10271036 /* maximum transfer unit */
@@ -1068,12 +1077,12 @@ err_t lpc_enetif_init(struct netif *netif)
10681077 err = sys_sem_new (& lpc_enetdata .TxCleanSem , 0 );
10691078 LWIP_ASSERT ("TxCleanSem creation error" , (err == ERR_OK ));
10701079 sys_thread_new ("txclean_thread" , packet_tx , netif -> state , DEFAULT_THREAD_STACKSIZE , TX_PRIORITY );
1071-
1080+
10721081 /* periodic PHY status update */
10731082 osTimerId phy_timer = osTimerCreate (osTimer (phy_update ), osTimerPeriodic , (void * )netif );
10741083 osTimerStart (phy_timer , 250 );
10751084#endif
1076-
1085+
10771086 return ERR_OK ;
10781087}
10791088
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