11/**
22 ******************************************************************************
3- * @file stm32f401xe .h
3+ * @file stm32f401xc .h
44 * @author MCD Application Team
5- * @version V2.1 .0
6- * @date 19-June-2014
7- * @brief CMSIS STM32F401xExx Device Peripheral Access Layer Header File.
5+ * @version V2.3 .0
6+ * @date 02-March-2015
7+ * @brief CMSIS STM32F401xCxx Device Peripheral Access Layer Header File.
88 *
99 * This file contains:
1010 * - Data structures and the address mapping for all peripherals
1414 ******************************************************************************
1515 * @attention
1616 *
17- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
17+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
1818 *
1919 * Redistribution and use in source and binary forms, with or without modification,
2020 * are permitted provided that the following conditions are met:
4545 * @{
4646 */
4747
48- /** @addtogroup stm32f401xe
48+ /** @addtogroup stm32f401xc
4949 * @{
5050 */
5151
52- #ifndef __STM32F401xE_H
53- #define __STM32F401xE_H
52+ #ifndef __STM32F401xC_H
53+ #define __STM32F401xC_H
5454
5555#ifdef __cplusplus
5656 extern "C" {
@@ -290,8 +290,7 @@ typedef struct
290290 __IO uint32_t PUPDR ; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
291291 __IO uint32_t IDR ; /*!< GPIO port input data register, Address offset: 0x10 */
292292 __IO uint32_t ODR ; /*!< GPIO port output data register, Address offset: 0x14 */
293- __IO uint16_t BSRRL ; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
294- __IO uint16_t BSRRH ; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
293+ __IO uint32_t BSRR ; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
295294 __IO uint32_t LCKR ; /*!< GPIO port configuration lock register, Address offset: 0x1C */
296295 __IO uint32_t AFR [2 ]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
297296} GPIO_TypeDef ;
@@ -536,7 +535,7 @@ typedef struct
536535 __IO uint32_t CFR ; /*!< WWDG Configuration register, Address offset: 0x04 */
537536 __IO uint32_t SR ; /*!< WWDG Status register, Address offset: 0x08 */
538537} WWDG_TypeDef ;
539-
538+
540539/**
541540 * @brief __USB_OTG_Core_register
542541 */
@@ -675,7 +674,7 @@ USB_OTG_HostChannelTypeDef;
675674#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
676675#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
677676#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
678- #define FLASH_END ((uint32_t)0x0807FFFF ) /*!< FLASH end address */
677+ #define FLASH_END ((uint32_t)0x0803FFFF ) /*!< FLASH end address */
679678
680679/* Legacy defines */
681680#define SRAM_BASE SRAM1_BASE
@@ -1423,6 +1422,9 @@ USB_OTG_HostChannelTypeDef;
14231422#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
14241423#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
14251424#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
1425+ #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
1426+ #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
1427+ #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
14261428
14271429/******************* Bit definition for EXTI_EMR register *******************/
14281430#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -1445,6 +1447,9 @@ USB_OTG_HostChannelTypeDef;
14451447#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
14461448#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
14471449#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
1450+ #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
1451+ #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
1452+ #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
14481453
14491454/****************** Bit definition for EXTI_RTSR register *******************/
14501455#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -1467,6 +1472,9 @@ USB_OTG_HostChannelTypeDef;
14671472#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
14681473#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
14691474#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
1475+ #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
1476+ #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
1477+ #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
14701478
14711479/****************** Bit definition for EXTI_FTSR register *******************/
14721480#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -1489,6 +1497,9 @@ USB_OTG_HostChannelTypeDef;
14891497#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
14901498#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
14911499#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
1500+ #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
1501+ #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
1502+ #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
14921503
14931504/****************** Bit definition for EXTI_SWIER register ******************/
14941505#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -1511,6 +1522,9 @@ USB_OTG_HostChannelTypeDef;
15111522#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
15121523#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
15131524#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
1525+ #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
1526+ #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
1527+ #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
15141528
15151529/******************* Bit definition for EXTI_PR register ********************/
15161530#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -1533,6 +1547,9 @@ USB_OTG_HostChannelTypeDef;
15331547#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
15341548#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
15351549#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
1550+ #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
1551+ #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
1552+ #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
15361553
15371554/******************************************************************************/
15381555/* */
@@ -1954,7 +1971,7 @@ USB_OTG_HostChannelTypeDef;
19541971#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
19551972#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
19561973
1957- /****************** Bit definition for GPIO_LCKR register ********************/
1974+ /****************** Bit definition for GPIO_LCKR register ********************* /
19581975#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
19591976#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
19601977#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
@@ -2125,7 +2142,7 @@ USB_OTG_HostChannelTypeDef;
21252142#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
21262143#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
21272144#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
2128- #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
2145+ #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
21292146#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
21302147#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
21312148
@@ -4511,14 +4528,14 @@ USB_OTG_HostChannelTypeDef;
45114528 ((INSTANCE) == I2C3))
45124529
45134530/******************************** I2S Instances *******************************/
4514- #define IS_I2S_INSTANCE (INSTANCE ) (((INSTANCE) == SPI2) || \
4531+ #define IS_I2S_ALL_INSTANCE (INSTANCE ) (((INSTANCE) == SPI2) || \
45154532 ((INSTANCE) == SPI3))
45164533
45174534/*************************** I2S Extended Instances ***************************/
4518- #define IS_I2S_INSTANCE_EXT (PERIPH ) (((INSTANCE) == SPI2) || \
4519- ((INSTANCE) == SPI3) || \
4520- ((INSTANCE) == I2S2ext) || \
4521- ((INSTANCE) == I2S3ext))
4535+ #define IS_I2S_ALL_INSTANCE_EXT (PERIPH ) (((INSTANCE) == SPI2) || \
4536+ ((INSTANCE) == SPI3) || \
4537+ ((INSTANCE) == I2S2ext) || \
4538+ ((INSTANCE) == I2S3ext))
45224539
45234540/****************************** RTC Instances *********************************/
45244541#define IS_RTC_ALL_INSTANCE (INSTANCE ) ((INSTANCE) == RTC)
@@ -4728,6 +4745,14 @@ USB_OTG_HostChannelTypeDef;
47284745/****************************** WWDG Instances ********************************/
47294746#define IS_WWDG_ALL_INSTANCE (INSTANCE ) ((INSTANCE) == WWDG)
47304747
4748+ /****************************** SDIO Instances ********************************/
4749+ #define IS_SDIO_ALL_INSTANCE (INSTANCE ) ((INSTANCE) == SDIO)
4750+
4751+ /****************************** USB Exported Constants ************************/
4752+ #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
4753+ #define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
4754+ #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
4755+ #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
47314756
47324757/**
47334758 * @}
@@ -4745,7 +4770,7 @@ USB_OTG_HostChannelTypeDef;
47454770}
47464771#endif /* __cplusplus */
47474772
4748- #endif /* __STM32F401xE_H */
4773+ #endif /* __STM32F401xC_H */
47494774
47504775
47514776
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