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Merge pull request #103 from 0xc0170/dev_kl46z
Dev kl46z
2 parents 17bdeb4 + f4591db commit 887fd2b

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6 files changed

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‎libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/MKL46Z4.h‎

Lines changed: 1874 additions & 233 deletions
Large diffs are not rendered by default.

‎libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/system_MKL46Z4.c‎

Lines changed: 26 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,37 +1,43 @@
11
/*
22
** ###################################################################
3-
** Processor: MKL46Z128VLK4
3+
** Processors: MKL46Z256VLH4
4+
** MKL46Z128VLH4
5+
** MKL46Z256VLL4
6+
** MKL46Z128VLL4
7+
** MKL46Z256VMC4
8+
** MKL46Z128VMC4
9+
**
410
** Compilers: ARM Compiler
511
** Freescale C/C++ for Embedded ARM
612
** GNU C Compiler
713
** IAR ANSI C/C++ Compiler for ARM
814
**
9-
** Reference manual: KL25RM, Rev.1, Jun 2012
10-
** Version: rev. 1.1, 2012-06-21
15+
** Reference manual: KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
16+
** Version: rev. 2.0, 2012-12-12
1117
**
1218
** Abstract:
1319
** Provides a system configuration function and a global variable that
1420
** contains the system frequency. It configures the device and initializes
1521
** the oscillator (PLL) that is part of the microcontroller device.
1622
**
17-
** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
23+
** Copyright: 2012 Freescale, Inc. All Rights Reserved.
1824
**
1925
** http: www.freescale.com
2026
** mail: [email protected]
2127
**
2228
** Revisions:
23-
** - rev. 1.0 (2012-06-13)
29+
** - rev. 1.0 (2012-10-16)
2430
** Initial version.
25-
** - rev. 1.1 (2012-06-21)
26-
** Update according to reference manual rev. 1.
31+
** - rev. 2.0 (2012-12-12)
32+
** Update to reference manual rev. 1.
2733
**
2834
** ###################################################################
2935
*/
3036

3137
/**
3238
* @file MKL46Z4
33-
* @version 1.1
34-
* @date 2012-06-21
39+
* @version 2.0
40+
* @date 2012-12-12
3541
* @brief Device specific configuration file for MKL46Z4 (implementation file)
3642
*
3743
* Provides a system configuration function and a global variable that contains
@@ -100,8 +106,8 @@ void SystemInit (void) {
100106
/* Switch to FEI Mode */
101107
/* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
102108
MCG->C1 = (uint8_t)0x06U;
103-
/* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
104-
MCG->C2 = (uint8_t)0x00U;
109+
/* MCG_C2: LOCRE0=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
110+
MCG->C2 &= (uint8_t)~(uint8_t)0xBFU;
105111
/* MCG->C4: DMX32=0,DRST_DRS=1 */
106112
MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
107113
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
@@ -124,11 +130,11 @@ void SystemInit (void) {
124130
/* PORTA->PCR19: ISF=0,MUX=0 */
125131
PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
126132
/* Switch to FBE Mode */
127-
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
128-
OSC0->CR = (uint8_t)0x89U;
129-
/* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
130-
MCG->C2 = (uint8_t)0x24U;
131-
/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
133+
/* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
134+
MCG->C2 = (uint8_t)((MCG->C2 & (uint8_t)~(uint8_t)0x9BU) | (uint8_t)0x24U);
135+
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=0 */
136+
OSC0->CR = (uint8_t)0x80U;
137+
/* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
132138
MCG->C1 = (uint8_t)0x9AU;
133139
/* MCG->C4: DMX32=0,DRST_DRS=0 */
134140
MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
@@ -162,10 +168,10 @@ void SystemInit (void) {
162168
/* PORTA->PCR19: ISF=0,MUX=0 */
163169
PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
164170
/* Switch to FBE Mode */
165-
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
166-
OSC0->CR = (uint8_t)0x89U;
167171
/* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
168172
MCG->C2 = (uint8_t)0x24U;
173+
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=0 */
174+
OSC0->CR = (uint8_t)0x80U;
169175
/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
170176
MCG->C1 = (uint8_t)0x9AU;
171177
/* MCG->C4: DMX32=0,DRST_DRS=0 */
@@ -179,8 +185,8 @@ void SystemInit (void) {
179185
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
180186
}
181187
/* Switch to BLPE Mode */
182-
/* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
183-
MCG->C2 = (uint8_t)0x26U;
188+
/* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
189+
MCG->C2 = (uint8_t)((MCG->C2 & (uint8_t)~(uint8_t)0x99U) | (uint8_t)0x26U);
184190
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
185191
}
186192
#endif /* (CLOCK_SETUP == 2) */

‎libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/system_MKL46Z4.h‎

Lines changed: 15 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,37 +1,43 @@
11
/*
22
** ###################################################################
3-
** Processor: MKL46Z128VLK4
3+
** Processors: MKL46Z256VLH4
4+
** MKL46Z128VLH4
5+
** MKL46Z256VLL4
6+
** MKL46Z128VLL4
7+
** MKL46Z256VMC4
8+
** MKL46Z128VMC4
9+
**
410
** Compilers: ARM Compiler
511
** Freescale C/C++ for Embedded ARM
612
** GNU C Compiler
713
** IAR ANSI C/C++ Compiler for ARM
814
**
9-
** Reference manual: KL25RM, Rev.1, Jun 2012
10-
** Version: rev. 1.1, 2012-06-21
15+
** Reference manual: KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
16+
** Version: rev. 2.0, 2012-12-12
1117
**
1218
** Abstract:
1319
** Provides a system configuration function and a global variable that
1420
** contains the system frequency. It configures the device and initializes
1521
** the oscillator (PLL) that is part of the microcontroller device.
1622
**
17-
** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
23+
** Copyright: 2012 Freescale, Inc. All Rights Reserved.
1824
**
1925
** http: www.freescale.com
2026
** mail: [email protected]
2127
**
2228
** Revisions:
23-
** - rev. 1.0 (2012-06-13)
29+
** - rev. 1.0 (2012-10-16)
2430
** Initial version.
25-
** - rev. 1.1 (2012-06-21)
26-
** Update according to reference manual rev. 1.
31+
** - rev. 2.0 (2012-12-12)
32+
** Update to reference manual rev. 1.
2733
**
2834
** ###################################################################
2935
*/
3036

3137
/**
3238
* @file MKL46Z4
33-
* @version 1.1
34-
* @date 2012-06-21
39+
* @version 2.0
40+
* @date 2012-12-12
3541
* @brief Device specific configuration file for MKL46Z4 (header file)
3642
*
3743
* Provides a system configuration function and a global variable that contains

‎libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/objects.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ struct pwmout_s {
4646
};
4747

4848
struct serial_s {
49-
UARTLP_Type *uart;
49+
UART0_Type *uart;
5050
int index;
5151
};
5252

‎libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/serial_api.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
7171
error("Serial pinout mapping failed");
7272
}
7373

74-
obj->uart = (UARTLP_Type *)uart;
74+
obj->uart = (UART0_Type *)uart;
7575
// enable clk
7676
switch (uart) {
7777
case UART_0: SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK | (1<<SIM_SOPT2_UART0SRC_SHIFT);
@@ -200,8 +200,8 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b
200200

201201
// enable 10bit mode if needed
202202
if (obj->index == 0) {
203-
obj->uart->C4 &= ~UARTLP_C4_M10_MASK;
204-
obj->uart->C4 |= (m10 << UARTLP_C4_M10_SHIFT);
203+
obj->uart->C4 &= ~UART0_C4_M10_MASK;
204+
obj->uart->C4 |= (m10 << UART0_C4_M10_SHIFT);
205205
}
206206

207207
// stop bits

‎libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/spi_api.c‎

Lines changed: 45 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -96,7 +96,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
9696

9797
// enable power and clocking
9898
switch ((int)obj->spi) {
99-
case SPI_0: SIM->SCGC5 |= 1 << 11; SIM->SCGC4 |= 1 << 22; break;
99+
case SPI_0: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 22; break;
100100
case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break;
101101
}
102102

@@ -110,6 +110,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
110110

111111
// enable SPI
112112
obj->spi->C1 |= SPI_C1_SPE_MASK;
113+
obj->spi->C2 &= ~SPI_C2_SPIMODE_MASK; //8bit
113114

114115
// pin out the spi pins
115116
pinmap_pinout(mosi, PinMap_SPI_MOSI);
@@ -124,8 +125,8 @@ void spi_free(spi_t *obj) {
124125
// [TODO]
125126
}
126127
void spi_format(spi_t *obj, int bits, int mode, int slave) {
127-
if (bits != 8) {
128-
error("Only 8bits SPI supported");
128+
if ((bits != 8) && (bits != 16)) {
129+
error("Only 8/16 bits SPI supported");
129130
}
130131

131132
if ((mode < 0) || (mode > 3)) {
@@ -141,6 +142,11 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
141142

142143
// write new value
143144
obj->spi->C1 |= c1_data;
145+
if (bits == 8) {
146+
obj->spi->C2 &= ~SPI_C2_SPIMODE_MASK;
147+
} else {
148+
obj->spi->C2 |= SPI_C2_SPIMODE_MASK;
149+
}
144150
}
145151

146152
void spi_frequency(spi_t *obj, int hz) {
@@ -184,24 +190,52 @@ static inline int spi_readable(spi_t * obj) {
184190
}
185191

186192
int spi_master_write(spi_t *obj, int value) {
187-
// wait tx buffer empty
188-
while(!spi_writeable(obj));
189-
obj->spi->D = (value & 0xff);
193+
int ret;
194+
if (obj->spi->C2 & SPI_C2_SPIMODE_MASK) {
195+
// 16bit
196+
while(!spi_writeable(obj));
197+
obj->spi->DL = (value & 0xff);
198+
obj->spi->DH = ((value >> 8) & 0xff);
199+
200+
// wait rx buffer full
201+
while (!spi_readable(obj));
202+
ret = obj->spi->DH;
203+
ret = (ret << 8) | obj->spi->DL;
204+
} else {
205+
//8bit
206+
while(!spi_writeable(obj));
207+
obj->spi->DL = (value & 0xff);
208+
209+
// wait rx buffer full
210+
while (!spi_readable(obj));
211+
ret = (obj->spi->DL & 0xff);
212+
}
190213

191-
// wait rx buffer full
192-
while (!spi_readable(obj));
193-
return obj->spi->D & 0xff;
214+
return ret;
194215
}
195216

196217
int spi_slave_receive(spi_t *obj) {
197218
return spi_readable(obj);
198219
}
199220

200221
int spi_slave_read(spi_t *obj) {
201-
return obj->spi->D;
222+
int ret;
223+
if (obj->spi->C2 & SPI_C2_SPIMODE_MASK) {
224+
ret = obj->spi->DH;
225+
ret = ((ret << 8) | obj->spi->DL);
226+
} else {
227+
ret = obj->spi->DL;
228+
}
229+
return ret;
202230
}
203231

204232
void spi_slave_write(spi_t *obj, int value) {
205233
while (!spi_writeable(obj));
206-
obj->spi->D = value;
234+
if (obj->spi->C2 & SPI_C2_SPIMODE_MASK) {
235+
obj->spi->DL = (value & 0xff);
236+
obj->spi->DH = ((value >> 8) & 0xff);
237+
} else {
238+
obj->spi->DL = value;
239+
}
240+
207241
}

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