Make changes for Cortex-A5 support

Author: Meano

hal/source/mbed_critical_section_api.c

@@ -26,7 +26,7 @@ static bool state_saved = false;
 
 static bool are_interrupts_enabled(void)
 {
-#if defined(__CORTEX_A9)
+#if defined(__CORTEX_A9) || defined(__CORTEX_A5)
     return ((__get_CPSR() & 0x80) == 0);
 #else
     return ((__get_PRIMASK() & 0x1) == 0);

platform/source/mbed_critical.c

@@ -27,7 +27,7 @@ static uint32_t critical_section_reentrancy_counter = 0;
 
 bool core_util_are_interrupts_enabled(void)
 {
-#if defined(__CORTEX_A9)
+#if defined(__CORTEX_A9) || defined(__CORTEX_A5)
     return ((__get_CPSR() & 0x80) == 0);
 #else
     return ((__get_PRIMASK() & 0x1) == 0);
@@ -36,7 +36,7 @@ bool core_util_are_interrupts_enabled(void)
 
 bool core_util_is_isr_active(void)
 {
-#if defined(__CORTEX_A9)
+#if defined(__CORTEX_A9) || defined(__CORTEX_A5)
     switch (__get_CPSR() & 0x1FU) {
         case CPSR_M_USR:
         case CPSR_M_SYS:

platform/source/mbed_wait_api_no_rtos.c

@@ -91,7 +91,7 @@ void wait_us(int us)
 #define LOOP_SCALER 2000
 #endif
 #elif defined __CORTEX_A
-#if __CORTEX_A == 9
+#if __CORTEX_A == 9 || __CORTEX_A == 5
 // Cortex-A9 can dual issue for 3 cycles per iteration (SUB,NOP) = 1, (NOP,BCS) = 2
 #define LOOP_SCALER 3000
 #endif

tools/cmake/cores/Cortex-A5.cmake

@@ -0,0 +1,31 @@
+# Copyright (c) 2020-2021 ARM Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
+    list(APPEND common_options
+        "-mthumb-interwork"
+        "-marm"
+        "-mfpu=vfpv3"
+        "-mfloat-abi=softfp"
+        "-mno-unaligned-access"
+        "-mcpu=cortex-a5"
+    )
+elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
+    list(APPEND common_options
+        "-mfpu=vfpv3"
+        "-mfloat-abi=hard"
+        "-mcpu=cortex-a5"
+    )
+endif()
+
+function(mbed_set_cpu_core_definitions target)
+    target_compile_definitions(${target}
+        INTERFACE
+            __CORTEX_A5
+            ARM_MATH_CA5
+            __FPU_PRESENT
+            __CMSIS_RTOS
+            __EVAL
+            __MBED_CMSIS_RTOS_CA5
+    )
+endfunction()

tools/cmake/mbed_toolchain.cmake

@@ -25,6 +25,8 @@ endfunction()
 # Set the system processor depending on the CPU core type
 if (MBED_CPU_CORE STREQUAL Cortex-A9)
     set(CMAKE_SYSTEM_PROCESSOR cortex-a9)
+elseif (MBED_CPU_CORE STREQUAL Cortex-A5)
+    set(CMAKE_SYSTEM_PROCESSOR cortex-a5)
 elseif (MBED_CPU_CORE STREQUAL Cortex-M0+)
     set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus)
 elseif (MBED_CPU_CORE STREQUAL Cortex-M0)

tools/targets/__init__.py

@@ -49,6 +49,7 @@
     "Cortex-M7F": ["M7", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M7", "CORTEX"],
     "Cortex-M7FD": ["M7", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M7",
                     "CORTEX"],
+    "Cortex-A5": ["A5", "CORTEX_A", "LIKE_CORTEX_A5", "CORTEX"],
     "Cortex-A9": ["A9", "CORTEX_A", "LIKE_CORTEX_A9", "CORTEX"],
     "Cortex-M23": ["M23", "CORTEX_M", "LIKE_CORTEX_M23", "CORTEX"],
     "Cortex-M23-NS": ["M23", "M23_NS", "CORTEX_M", "LIKE_CORTEX_M23",
@@ -74,6 +75,7 @@
     "Cortex-M7": 7,
     "Cortex-M7F": 7,
     "Cortex-M7FD": 7,
+    "Cortex-A5": 7,
     "Cortex-A9": 7,
     "Cortex-M23": 8,
     "Cortex-M23-NS": 8,

tools/toolchains/mbed_toolchain.py

@@ -86,6 +86,8 @@
                         "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
     "Cortex-M7FD":     ["__CORTEX_M7", "ARM_MATH_CM7", "__FPU_PRESENT=1",
                         "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+    "Cortex-A5":       ["__CORTEX_A5", "ARM_MATH_CA5", "__FPU_PRESENT",
+                        "__CMSIS_RTOS", "__EVAL", "__MBED_CMSIS_RTOS_CA5"],
     "Cortex-A9":       ["__CORTEX_A9", "ARM_MATH_CA9", "__FPU_PRESENT",
                         "__CMSIS_RTOS", "__EVAL", "__MBED_CMSIS_RTOS_CA9"],
     "Cortex-M23-NS":   ["__CORTEX_M23", "ARM_MATH_ARMV8MBL", "DOMAIN_NS=1",