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0xc01700xc0170
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Merge pull request #11301 from jeromecoutant/PR_L4R
STM32L4+ : increase system clock from 80 MHz to 120 MHz
2 parents 421ad37 + 680e0fc commit 7e179f5

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2 files changed

+60
-60
lines changed

2 files changed

+60
-60
lines changed

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/system_clock.c‎

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -22,10 +22,10 @@
2222
* | 3- USE_PLL_HSI (internal 16 MHz)
2323
* | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
2424
*-----------------------------------------------------------------------------
25-
* SYSCLK(MHz) | 80
26-
* AHBCLK (MHz) | 80
27-
* APB1CLK (MHz) | 80
28-
* APB2CLK (MHz) | 80
25+
* SYSCLK(MHz) | 120
26+
* AHBCLK (MHz) | 120
27+
* APB1CLK (MHz) | 120
28+
* APB2CLK (MHz) | 120
2929
* USB capable | YES
3030
*-----------------------------------------------------------------------------
3131
**/
@@ -136,22 +136,22 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
136136
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
137137
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
138138
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
139-
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
140-
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
141-
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
139+
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
140+
RCC_OscInitStruct.PLL.PLLN = 30; // VCO output clock = 240 MHz (8 MHz * 30)
141+
RCC_OscInitStruct.PLL.PLLP = 7;
142142
RCC_OscInitStruct.PLL.PLLQ = 2;
143-
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
143+
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 120 MHz (240 MHz / 2)
144144

145145
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
146146
return 0; // FAIL
147147
}
148148

149149
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
150150
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
151-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
152-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
153-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
154-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
151+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 120 MHz
152+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 120 MHz
153+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 120 MHz
154+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 120 MHz
155155
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
156156
return 0; // FAIL
157157
}
@@ -160,9 +160,9 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
160160
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
161161
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
162162
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
163-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
163+
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; // 96 MHz
164164
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
165-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
165+
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; // 48 MHz
166166
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
167167
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
168168
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
@@ -217,21 +217,21 @@ uint8_t SetSysClock_PLL_HSI(void)
217217
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
218218
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
219219
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
220-
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
221-
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
222-
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
220+
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
221+
RCC_OscInitStruct.PLL.PLLN = 30; // VCO output clock = 240 MHz (8 MHz * 30)
222+
RCC_OscInitStruct.PLL.PLLP = 7;
223223
RCC_OscInitStruct.PLL.PLLQ = 2;
224-
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
224+
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 120 MHz (240 MHz / 2)
225225
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
226226
return 0; // FAIL
227227
}
228228

229229
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
230230
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
231-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
232-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
233-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
234-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
231+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 120 MHz
232+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 120 MHz
233+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 120 MHz
234+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 120 MHz
235235
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
236236
return 0; // FAIL
237237
}
@@ -300,10 +300,10 @@ uint8_t SetSysClock_PLL_MSI(void)
300300
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
301301
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
302302
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
303-
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
304-
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
305-
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
306-
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
303+
RCC_OscInitStruct.PLL.PLLN = 30; /* 240 MHz */
304+
RCC_OscInitStruct.PLL.PLLP = 5; /* 48 MHz */
305+
RCC_OscInitStruct.PLL.PLLQ = 2; /* 120 MHz */
306+
RCC_OscInitStruct.PLL.PLLR = 2; /* 120 MHz */
307307
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
308308
return 0; // FAIL
309309
}
@@ -316,10 +316,10 @@ uint8_t SetSysClock_PLL_MSI(void)
316316

317317
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
318318
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
319-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
320-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
321-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
322-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
319+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 120 MHz */
320+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 120 MHz */
321+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 120 MHz */
322+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 120 MHz */
323323
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
324324
return 0; // FAIL
325325
}

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/system_clock.c‎

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -22,10 +22,10 @@
2222
* | 3- USE_PLL_HSI (internal 16 MHz)
2323
* | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
2424
*-----------------------------------------------------------------------------
25-
* SYSCLK(MHz) | 80
26-
* AHBCLK (MHz) | 80
27-
* APB1CLK (MHz) | 80
28-
* APB2CLK (MHz) | 80
25+
* SYSCLK(MHz) | 120
26+
* AHBCLK (MHz) | 120
27+
* APB1CLK (MHz) | 120
28+
* APB2CLK (MHz) | 120
2929
* USB capable | YES
3030
*-----------------------------------------------------------------------------
3131
**/
@@ -136,22 +136,22 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
136136
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
137137
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
138138
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
139-
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
140-
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
141-
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
139+
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
140+
RCC_OscInitStruct.PLL.PLLN = 30; // VCO output clock = 240 MHz (8 MHz * 30)
141+
RCC_OscInitStruct.PLL.PLLP = 7;
142142
RCC_OscInitStruct.PLL.PLLQ = 2;
143-
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
143+
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 120 MHz (240 MHz / 2)
144144

145145
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
146146
return 0; // FAIL
147147
}
148148

149149
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
150150
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
151-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
152-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
153-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
154-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
151+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 120 MHz
152+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 120 MHz
153+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 120 MHz
154+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 120 MHz
155155
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
156156
return 0; // FAIL
157157
}
@@ -160,9 +160,9 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
160160
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
161161
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
162162
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
163-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
163+
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; // 96 MHz
164164
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
165-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
165+
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; // 48 MHz
166166
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
167167
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
168168
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
@@ -217,21 +217,21 @@ uint8_t SetSysClock_PLL_HSI(void)
217217
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
218218
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
219219
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
220-
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
221-
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
222-
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
220+
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
221+
RCC_OscInitStruct.PLL.PLLN = 30; // VCO output clock = 240 MHz (8 MHz * 30)
222+
RCC_OscInitStruct.PLL.PLLP = 7;
223223
RCC_OscInitStruct.PLL.PLLQ = 2;
224-
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
224+
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 120 MHz (240 MHz / 2)
225225
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
226226
return 0; // FAIL
227227
}
228228

229229
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
230230
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
231-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
232-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
233-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
234-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
231+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 120 MHz
232+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 120 MHz
233+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 120 MHz
234+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 120 MHz
235235
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
236236
return 0; // FAIL
237237
}
@@ -300,10 +300,10 @@ uint8_t SetSysClock_PLL_MSI(void)
300300
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
301301
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
302302
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
303-
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
304-
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
305-
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
306-
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
303+
RCC_OscInitStruct.PLL.PLLN = 30; /* 240 MHz */
304+
RCC_OscInitStruct.PLL.PLLP = 5; /* 48 MHz */
305+
RCC_OscInitStruct.PLL.PLLQ = 2; /* 120 MHz */
306+
RCC_OscInitStruct.PLL.PLLR = 2; /* 120 MHz */
307307
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
308308
return 0; // FAIL
309309
}
@@ -316,10 +316,10 @@ uint8_t SetSysClock_PLL_MSI(void)
316316

317317
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
318318
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
319-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
320-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
321-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
322-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
319+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 120 MHz */
320+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 120 MHz */
321+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 120 MHz */
322+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 120 MHz */
323323
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
324324
return 0; // FAIL
325325
}

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